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-rw-r--r--board/hermes/flash.c24
-rw-r--r--board/hermes/hermes.c22
2 files changed, 23 insertions, 23 deletions
diff --git a/board/hermes/flash.c b/board/hermes/flash.c
index 799fe83..888231c 100644
--- a/board/hermes/flash.c
+++ b/board/hermes/flash.c
@@ -24,7 +24,7 @@
#include <common.h>
#include <mpc8xx.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
@@ -38,13 +38,13 @@ static void flash_get_offsets (ulong base, flash_info_t *info);
unsigned long flash_init (void)
{
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size;
int i;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -58,20 +58,20 @@ unsigned long flash_init (void)
}
/* Remap FLASH according to real size */
- memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
- memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) |
+ memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+ memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
(memctl->memc_br0 & ~(BR_BA_MSK));
/* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+ size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
- flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+ flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
@@ -376,7 +376,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
last = start;
addr = (vu_char*)(info->start[l_sect]);
while ((addr[0] & 0x80) != 0x80) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@@ -449,7 +449,7 @@ static int write_byte (flash_info_t *info, ulong dest, uchar data)
/* data polling for D7 */
start = get_timer (0);
while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c
index f9b5720..9a3e5f6 100644
--- a/board/hermes/hermes.c
+++ b/board/hermes/hermes.c
@@ -136,7 +136,7 @@ int checkboard (void)
phys_size_t initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size, size8, size9;
@@ -153,8 +153,8 @@ phys_size_t initdram (int board_type)
/*
* Map controller banks 1 to the SDRAM banks at preliminary address
*/
- memctl->memc_or1 = CFG_OR1_PRELIM;
- memctl->memc_br1 = CFG_BR1_PRELIM;
+ memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+ memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
/* HERMES-PRO boards have only one bank SDRAM */
@@ -179,7 +179,7 @@ phys_size_t initdram (int board_type)
*
* try 8 column mode
*/
- size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
+ size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
@@ -187,7 +187,7 @@ phys_size_t initdram (int board_type)
/*
* try 9 column mode
*/
- size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
+ size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
@@ -195,7 +195,7 @@ phys_size_t initdram (int board_type)
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
} else { /* back to 8 columns */
size = size8;
- memctl->memc_mamr = CFG_MAMR_8COL;
+ memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
udelay (500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
}
@@ -203,7 +203,7 @@ phys_size_t initdram (int board_type)
udelay (1000);
memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
- memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+ memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
udelay (10000);
@@ -223,7 +223,7 @@ phys_size_t initdram (int board_type)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_mamr = mamr_value;
@@ -264,7 +264,7 @@ static long int dram_size (long int mamr_value, long int *base,
static ulong board_init (void)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
ulong reg, revision, speed = 100;
int ethspeed;
char *s;
@@ -403,7 +403,7 @@ static ulong board_init (void)
*/
void hermes_start_lxt980 (int speed)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm);
volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]);
volatile cbd_t *bd;
@@ -595,7 +595,7 @@ static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
void show_boot_progress (int status)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
if (status < -32) status = -1; /* let things compatible */
status ^= 0x0F;
generated by cgit v1.1 at 2024-11-10 04:18:49 +0000