summaryrefslogtreecommitdiff
path: root/board/gdsys
diff options
context:
space:
mode:
Diffstat (limited to 'board/gdsys')
-rw-r--r--board/gdsys/dlvision/dlvision.c2
-rw-r--r--board/gdsys/gdppc440etx/gdppc440etx.c52
-rw-r--r--board/gdsys/intip/Makefile (renamed from board/gdsys/compactcenter/Makefile)0
-rw-r--r--board/gdsys/intip/chip_config.c (renamed from board/gdsys/compactcenter/chip_config.c)0
-rw-r--r--board/gdsys/intip/config.mk (renamed from board/gdsys/compactcenter/config.mk)0
-rw-r--r--board/gdsys/intip/init.S (renamed from board/gdsys/compactcenter/init.S)0
-rw-r--r--board/gdsys/intip/intip.c (renamed from board/gdsys/compactcenter/compactcenter.c)4
-rw-r--r--board/gdsys/intip/u-boot.lds (renamed from board/gdsys/compactcenter/u-boot.lds)2
-rw-r--r--board/gdsys/neo/neo.c2
9 files changed, 31 insertions, 31 deletions
diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c
index 4ec1cdb..5246bc8 100644
--- a/board/gdsys/dlvision/dlvision.c
+++ b/board/gdsys/dlvision/dlvision.c
@@ -48,7 +48,7 @@ int board_early_init_f(void)
* EBC Configuration Register: set ready timeout to 512 ebc-clks
* -> ca. 15 us
*/
- mtebc(epcr, 0xa8400000); /* ebc always driven */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
/*
* setup io-latches
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
index a661057..27c159b 100644
--- a/board/gdsys/gdppc440etx/gdppc440etx.c
+++ b/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -42,8 +42,8 @@ int board_early_init_f(void)
/*
* Setup the external bus controller/chip selects
*/
- mfebc(xbcfg, reg);
- mtebc(xbcfg, reg | 0x04000000); /* Set ATC */
+ mfebc(EBC0_CFG, reg);
+ mtebc(EBC0_CFG, reg | 0x04000000); /* Set ATC */
/*
* Setup the GPIO pins
@@ -102,10 +102,10 @@ int board_early_init_f(void)
/*
* Setup other serial configuration
*/
- mfsdr(sdr_pci0, reg);
- mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
- mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
- mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
+ mfsdr(SDR0_PCI0, reg);
+ mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
+ mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
+ mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
return 0;
}
@@ -117,7 +117,7 @@ int misc_init_r(void)
uint sz;
/* Re-do sizing to get full correct info */
- mfebc(pb0cr, pbcr);
+ mfebc(PB0CR, pbcr);
if (gd->bd->bi_flashsize > 0x08000000)
panic("Max. flash banksize is 128 MB!\n");
@@ -127,7 +127,7 @@ int misc_init_r(void)
sz <<= 1;
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
- mtebc(pb0cr, pbcr);
+ mtebc(PB0CR, pbcr);
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
@@ -178,35 +178,35 @@ int pci_pre_init(struct pci_controller *hose)
* Set priority for all PLB3 devices to 0.
* Set PLB3 arbiter to fair mode.
*/
- mfsdr(sdr_amp1, addr);
- mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(plb3_acr);
- mtdcr(plb3_acr, addr | 0x80000000);
+ mfsdr(SD0_AMP1, addr);
+ mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(PLB3_ACR);
+ mtdcr(PLB3_ACR, addr | 0x80000000);
/*
* Set priority for all PLB4 devices to 0.
*/
- mfsdr(sdr_amp0, addr);
- mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
- addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
- mtdcr(plb4_acr, addr);
+ mfsdr(SD0_AMP0, addr);
+ mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
+ addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
+ mtdcr(PLB4_ACR, addr);
/*
* Set Nebula PLB4 arbiter to fair mode.
*/
/* Segment0 */
- addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
- addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
- addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
- addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
- mtdcr(plb0_acr, addr);
+ addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
+ addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
+ addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
+ addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
+ mtdcr(PLB0_ACR, addr);
/* Segment1 */
- addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
- addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
- addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
- addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
- mtdcr(plb1_acr, addr);
+ addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
+ addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
+ addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
+ addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
+ mtdcr(PLB1_ACR, addr);
/* enable 66 MHz ext. Clock */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000);
diff --git a/board/gdsys/compactcenter/Makefile b/board/gdsys/intip/Makefile
index 12f8a64..12f8a64 100644
--- a/board/gdsys/compactcenter/Makefile
+++ b/board/gdsys/intip/Makefile
diff --git a/board/gdsys/compactcenter/chip_config.c b/board/gdsys/intip/chip_config.c
index e46f4d8..e46f4d8 100644
--- a/board/gdsys/compactcenter/chip_config.c
+++ b/board/gdsys/intip/chip_config.c
diff --git a/board/gdsys/compactcenter/config.mk b/board/gdsys/intip/config.mk
index 56e397d..56e397d 100644
--- a/board/gdsys/compactcenter/config.mk
+++ b/board/gdsys/intip/config.mk
diff --git a/board/gdsys/compactcenter/init.S b/board/gdsys/intip/init.S
index e205c9d..e205c9d 100644
--- a/board/gdsys/compactcenter/init.S
+++ b/board/gdsys/intip/init.S
diff --git a/board/gdsys/compactcenter/compactcenter.c b/board/gdsys/intip/intip.c
index f448ef9..0de1be8 100644
--- a/board/gdsys/compactcenter/compactcenter.c
+++ b/board/gdsys/intip/intip.c
@@ -129,7 +129,7 @@ int checkboard(void)
#ifdef CONFIG_DEVCONCENTER
printf("Board: DevCon-Center");
#else
- printf("Board: CompactCenter");
+ printf("Board: Intip");
#endif
if (s != NULL) {
@@ -215,7 +215,7 @@ int board_early_init_r(void)
EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB;
/* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */
- mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L
+ mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L
| bxcr_bw
| EBC_BXCR_BU_RW
| EBC_BXCR_BW_16BIT);
diff --git a/board/gdsys/compactcenter/u-boot.lds b/board/gdsys/intip/u-boot.lds
index 0c95d5c..c1cbd1c 100644
--- a/board/gdsys/compactcenter/u-boot.lds
+++ b/board/gdsys/intip/u-boot.lds
@@ -66,7 +66,7 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/gdsys/compactcenter/init.o (.text)
+ board/gdsys/intip/init.o (.text)
*(.text)
*(.fixup)
diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c
index 817ce17..628ce3d 100644
--- a/board/gdsys/neo/neo.c
+++ b/board/gdsys/neo/neo.c
@@ -43,7 +43,7 @@ int board_early_init_f(void)
* EBC Configuration Register: set ready timeout to 512 ebc-clks
* -> ca. 15 us
*/
- mtebc(epcr, 0xa8400000); /* ebc always driven */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}
generated by cgit v1.1 at 2024-12-12 17:14:57 +0000