diff options
Diffstat (limited to 'board/gdsys')
| -rw-r--r-- | board/gdsys/405ep/405ep.c | 42 | ||||
| -rw-r--r-- | board/gdsys/405ep/405ep.h | 10 | ||||
| -rw-r--r-- | board/gdsys/405ep/Makefile | 1 | ||||
| -rw-r--r-- | board/gdsys/405ep/dlvision-10g.c | 36 | ||||
| -rw-r--r-- | board/gdsys/405ep/io.c | 34 | ||||
| -rw-r--r-- | board/gdsys/405ep/iocon.c | 34 | ||||
| -rw-r--r-- | board/gdsys/405ep/neo.c | 161 | ||||
| -rw-r--r-- | board/gdsys/neo/Makefile | 45 | ||||
| -rw-r--r-- | board/gdsys/neo/neo.c | 102 |
9 files changed, 293 insertions, 172 deletions
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index 8b80533..bea671e 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -28,12 +28,9 @@ #include <asm/ppc4xx-gpio.h> #include <asm/global_data.h> +#include "405ep.h" #include <gdsys_fpga.h> -#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) -#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) -#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) - #define REFLECTION_TESTPATTERN 0xdede #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff) @@ -55,7 +52,6 @@ void print_fpga_state(unsigned dev) int board_early_init_f(void) { unsigned k; - unsigned ctr; for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) gd->fpga_state[k] = 0; @@ -73,26 +69,29 @@ int board_early_init_f(void) * -> ca. 15 us */ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ + return 0; +} - /* - * setup io-latches for reset - */ - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); +int board_early_init_r(void) +{ + unsigned k; + unsigned ctr; - /* - * set "startup-finished"-gpios - */ - gpio_write_bit(21, 0); - gpio_write_bit(22, 1); + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) + gd->fpga_state[k] = 0; /* - * wait for fpga-done + * reset FPGA */ + gd405ep_init(); + + gd405ep_set_fpga_reset(1); + + gd405ep_setup_hw(); + for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ctr = 0; - while (!(in_le16((void *)LATCH2_BASE) - & CONFIG_SYS_FPGA_DONE(k))) { + while (!gd405ep_get_fpga_done(k)) { udelay(100000); if (ctr++ > 5) { gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED; @@ -101,12 +100,9 @@ int board_early_init_f(void) } } - /* - * setup io-latches for boot (stop reset) - */ udelay(10); - out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); - out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + + gd405ep_set_fpga_reset(0); for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k); diff --git a/board/gdsys/405ep/405ep.h b/board/gdsys/405ep/405ep.h new file mode 100644 index 0000000..5647dbc --- /dev/null +++ b/board/gdsys/405ep/405ep.h @@ -0,0 +1,10 @@ +#ifndef __405EP_H_ +#define __405EP_H_ + +/* functions to be provided by board implementation */ +void gd405ep_init(void); +void gd405ep_set_fpga_reset(unsigned state); +void gd405ep_setup_hw(void); +int gd405ep_get_fpga_done(unsigned fpga); + +#endif /* __405EP_H_ */ diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile index feb5cec..38e5ea4 100644 --- a/board/gdsys/405ep/Makefile +++ b/board/gdsys/405ep/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +COBJS-$(CONFIG_NEO) += neo.o COBJS-$(CONFIG_IO) += io.o COBJS-$(CONFIG_IOCON) += iocon.o COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index f55afbd..adaffb2 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -27,15 +27,18 @@ #include <asm/io.h> #include <asm/ppc4xx-gpio.h> +#include "405ep.h" #include <gdsys_fpga.h> #include "../common/osd.h" +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) -#define LATCH2_MC2_PRESENT_N 0x0080 - #define LATCH3_BASE (CONFIG_SYS_LATCH_BASE + 0x300) +#define LATCH2_MC2_PRESENT_N 0x0080 + enum { UNITTYPE_VIDEO_USER = 0, UNITTYPE_MAIN_USER = 1, @@ -261,3 +264,32 @@ int last_stage_init(void) return 0; } + +void gd405ep_init(void) +{ +} + +void gd405ep_set_fpga_reset(unsigned state) +{ + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } +} + +void gd405ep_setup_hw(void) +{ + /* + * set "startup-finished"-gpios + */ + gpio_write_bit(21, 0); + gpio_write_bit(22, 1); +} + +int gd405ep_get_fpga_done(unsigned fpga) +{ + return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); +} diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c index db1ea7f..ac4cefd 100644 --- a/board/gdsys/405ep/io.c +++ b/board/gdsys/405ep/io.c @@ -29,8 +29,13 @@ #include <miiphy.h> +#include "405ep.h" #include <gdsys_fpga.h> +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) + #define PHYREG_CONTROL 0 #define PHYREG_PAGE_ADDRESS 22 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16 @@ -175,3 +180,32 @@ int last_stage_init(void) return 0; } + +void gd405ep_init(void) +{ +} + +void gd405ep_set_fpga_reset(unsigned state) +{ + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } +} + +void gd405ep_setup_hw(void) +{ + /* + * set "startup-finished"-gpios + */ + gpio_write_bit(21, 0); + gpio_write_bit(22, 1); +} + +int gd405ep_get_fpga_done(unsigned fpga) +{ + return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); +} diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index ce53340..ed27791 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -27,10 +27,15 @@ #include <asm/io.h> #include <asm/ppc4xx-gpio.h> +#include "405ep.h" #include <gdsys_fpga.h> #include "../common/osd.h" +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) + enum { UNITTYPE_MAIN_SERVER = 0, UNITTYPE_MAIN_USER = 1, @@ -231,3 +236,32 @@ int fpga_gpio_get(int pin) { return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin; } + +void gd405ep_init(void) +{ +} + +void gd405ep_set_fpga_reset(unsigned state) +{ + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } +} + +void gd405ep_setup_hw(void) +{ + /* + * set "startup-finished"-gpios + */ + gpio_write_bit(21, 0); + gpio_write_bit(22, 1); +} + +int gd405ep_get_fpga_done(unsigned fpga) +{ + return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga); +} diff --git a/board/gdsys/405ep/neo.c b/board/gdsys/405ep/neo.c new file mode 100644 index 0000000..f38edd2 --- /dev/null +++ b/board/gdsys/405ep/neo.c @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2011 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/ppc4xx-gpio.h> +#include <dtt.h> + +#include "405ep.h" +#include <gdsys_fpga.h> + +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE) +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100) +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200) + +enum { + UNITTYPE_CCX16 = 1, + UNITTYPE_CCIP216 = 2, +}; + +enum { + HWVER_300 = 3, +}; + +int misc_init_r(void) +{ + /* startup fans */ + dtt_init(); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + puts("Board: CATCenter Neo"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +static void print_fpga_info(void) +{ + ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0); + u16 versions = in_le16(&fpga->versions); + u16 fpga_version = in_le16(&fpga->fpga_version); + u16 fpga_features = in_le16(&fpga->fpga_features); + int fpga_state = get_fpga_state(0); + unsigned unit_type; + unsigned hardware_version; + unsigned feature_channels; + + puts("FPGA: "); + if (fpga_state & FPGA_STATE_DONE_FAILED) { + printf(" done timed out\n"); + return; + } + + if (fpga_state & FPGA_STATE_REFLECTION_FAILED) { + printf(" refelectione test failed\n"); + return; + } + + unit_type = (versions & 0xf000) >> 12; + hardware_version = versions & 0x000f; + feature_channels = fpga_features & 0x007f; + + switch (unit_type) { + case UNITTYPE_CCX16: + printf("CCX-Switch"); + break; + + default: + printf("UnitType %d(not supported)", unit_type); + break; + } + + switch (hardware_version) { + case HWVER_300: + printf(" HW-Ver 3.00-3.12\n"); + break; + + default: + printf(" HW-Ver %d(not supported)\n", + hardware_version); + break; + } + + printf(" FPGA V %d.%02d, features:", + fpga_version / 100, fpga_version % 100); + + printf(" %d channel(s)\n", feature_channels); +} + +int last_stage_init(void) +{ + print_fpga_info(); + + return 0; +} + +void gd405ep_init(void) +{ +} + +void gd405ep_set_fpga_reset(unsigned state) +{ + if (state) { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET); + } else { + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT); + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT); + } +} + +void gd405ep_setup_hw(void) +{ + /* + * set "startup-finished"-gpios + */ + gpio_write_bit(21, 0); + gpio_write_bit(22, 1); +} + +int gd405ep_get_fpga_done(unsigned fpga) +{ + /* + * Neo hardware has no FPGA-DONE GPIO + */ + return 1; +} diff --git a/board/gdsys/neo/Makefile b/board/gdsys/neo/Makefile deleted file mode 100644 index dc5b5b8..0000000 --- a/board/gdsys/neo/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS = $(BOARD).o -SOBJS = - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c deleted file mode 100644 index d21d599..0000000 --- a/board/gdsys/neo/neo.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <asm/processor.h> -#include <asm/io.h> - -#define HWTYPE_CCX16 1 -#define HWREV_300 3 - -int board_early_init_f(void) -{ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - mtdcr(UIC0ER, 0x00000000); /* disable all ints */ - mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */ - mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */ - mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */ - mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */ - mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */ - - /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks - * -> ca. 15 us - */ - mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ - - return 0; -} - -/* - * Check Board Identity: - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - u16 val = in_le16((void *)CONFIG_FPGA_BASE + 2); - u8 unit_type; - u8 hardware_cpu_ports; - u8 hardware_con_ports; - u8 hardware_version; - - printf("Board: CATCenter Neo"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - puts("\n "); - - unit_type = (val & 0xf000) >> 12; - hardware_cpu_ports = ((val & 0x0f00) >> 8) * 8; - hardware_con_ports = ((val & 0x00f0) >> 4) * 2; - hardware_version = val & 0x000f; - - switch (unit_type) { - case HWTYPE_CCX16: - printf("CCX16-FPGA (80 UARTs)"); - break; - - default: - printf("UnitType %d, unsupported", unit_type); - break; - } - - printf(", %d cpu ports, %d console ports,", - hardware_cpu_ports, hardware_con_ports); - - switch (hardware_version) { - case HWREV_300: - printf(" HW-Ver 3.00\n"); - break; - - default: - printf(" HW-Ver %d, unsupported\n", - hardware_version); - break; - } - - return 0; -} |