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-rw-r--r--board/gdsys/405ep/iocon.c14
-rw-r--r--board/gdsys/405ex/io64.c4
-rw-r--r--board/gdsys/common/Makefile2
-rw-r--r--board/gdsys/common/dp501.c35
-rw-r--r--board/gdsys/common/osd.c189
-rw-r--r--board/gdsys/p1022/controlcenterd-id.c15
-rw-r--r--board/gdsys/p1022/controlcenterd.c12
-rw-r--r--board/gdsys/p1022/sdhc_boot.c2
8 files changed, 148 insertions, 125 deletions
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 7a98e41..1bac970 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -374,11 +374,12 @@ int last_stage_init(void)
FPGA_GET_REG(0, fpga_features, &fpga_features);
- if (!legacy)
- ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+ if (!legacy) {
+ /* Turn on Parade DP501 */
+ pca9698_direction_output(0x20, 9, 1);
- print_fpga_info(0, ch0_rgmii2_present);
- osd_probe(0);
+ ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
+ }
/* wait for FPGA done */
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
@@ -408,13 +409,16 @@ int last_stage_init(void)
}
}
- /* wait for slave-PLLs to be up and running */
+ /* give slave-PLLs and Parade DP501 some time to be up and running */
udelay(500000);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
mclink_fpgacount = 0;
+ print_fpga_info(0, ch0_rgmii2_present);
+ osd_probe(0);
+
if (slaves <= 0)
return 0;
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
index 2f8e306..3a075c4 100644
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
@@ -287,7 +287,7 @@ int last_stage_init(void)
for (fpga = 0; fpga < 2; ++fpga) {
for (k = 0; k < 32; ++k) {
u16 status;
- FPGA_GET_REG(k, ch[k].status_int, &status);
+ FPGA_GET_REG(fpga, ch[k].status_int, &status);
if (!(status & (1 << 4))) {
failed = 1;
printf("fpga %d channel %d: no serdes lock\n",
@@ -304,7 +304,7 @@ int last_stage_init(void)
for (fpga = 0; fpga < 2; ++fpga) {
for (k = 0; k < 32; ++k) {
u16 status;
- FPGA_GET_REG(k, hicb_ch[k].status_int, &status);
+ FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status);
if (status)
printf("fpga %d hicb %d: hicb status %04x\n",
fpga, k, status);
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index fb841e0..7f8b427 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -8,6 +8,6 @@
obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
obj-$(CONFIG_IO) += miiphybb.o
obj-$(CONFIG_IO64) += miiphybb.o
-obj-$(CONFIG_IOCON) += osd.o mclink.o
+obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o
obj-$(CONFIG_DLVISION_10G) += osd.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index 52f3ea1..7eb15ed 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -54,14 +54,39 @@ static void dp501_link_training(u8 addr)
void dp501_powerup(u8 addr)
{
dp501_clrbits(addr, 0x0a, 0x30); /* power on encoder */
+ dp501_setbits(addr, 0x0a, 0x0e); /* block HDCP and MCCS on I2C bride*/
i2c_reg_write(addr, 0x27, 0x30); /* Hardware auto detect DVO timing */
dp501_setbits(addr, 0x72, 0x80); /* DPCD read enable */
dp501_setbits(addr, 0x30, 0x20); /* RS polynomial select */
i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+ dp501_clrbits(addr, 0x60, 0x20); /* Enable scrambling */
+
+#ifdef CONFIG_SYS_DP501_VCAPCTRL0
+ i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
+#else
i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
+#endif
+
+#ifdef CONFIG_SYS_DP501_DIFFERENTIAL
+ i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
+ i2c_reg_write(addr + 2, 0x25, 0x04);
+ i2c_reg_write(addr + 2, 0x26, 0x10);
+#else
i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
+#endif
+
+ i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
+ i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
+ i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
+ i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
+ dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
+ i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
+ i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
+ i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
if (dp501_detect_cable_adapter(addr)) {
printf("DVI/HDMI cable adapter detected\n");
@@ -69,16 +94,6 @@ void dp501_powerup(u8 addr)
dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
} else {
printf("no DVI/HDMI cable adapter detected\n");
- i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
- i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
- i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
- i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
- dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
- i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
- i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
- i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
dp501_link_training(addr);
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index c49cd9a..1c765e4 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -9,6 +9,7 @@
#include <i2c.h>
#include <malloc.h>
+#include "dp501.h"
#include <gdsys_fpga.h>
#define CH7301_I2C_ADDR 0x75
@@ -24,6 +25,8 @@
#define SIL1178_MASTER_I2C_ADDRESS 0x38
#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+#define DP501_I2C_ADDR 0x08
+
#define PIXCLK_640_480_60 25180000
enum {
@@ -54,51 +57,23 @@ u16 *buf;
unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
-#ifdef CONFIG_SYS_CH7301
-int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
#endif
-#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
-static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
-{
- u16 val;
-
- do {
- FPGA_GET_REG(screen, extended_interrupt, &val);
- } while (val & (1 << 12));
-
- FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8));
- FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1));
-}
+#ifdef CONFIG_SYS_CH7301_I2C
+int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
+#endif
-static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
-{
- unsigned int ctr = 0;
- u16 val;
-
- do {
- FPGA_GET_REG(screen, extended_interrupt, &val);
- } while (val & (1 << 12));
-
- FPGA_SET_REG(screen, extended_interrupt, 1 << 14);
- FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg);
- FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1));
-
- FPGA_GET_REG(screen, extended_interrupt, &val);
- while (!(val & (1 << 14))) {
- udelay(100000);
- if (ctr++ > 5) {
- printf("iic receive timeout\n");
- break;
- }
- FPGA_GET_REG(screen, extended_interrupt, &val);
- }
+#ifdef CONFIG_SYS_SIL1178_I2C
+int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
+#endif
- FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val);
- return val >> 8;
-}
+#ifdef CONFIG_SYS_DP501_I2C
+int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
#endif
+
#ifdef CONFIG_SYS_MPC92469AC
static void mpc92469ac_calc_parameters(unsigned int fout,
unsigned int *post_div, unsigned int *feedback_div)
@@ -151,9 +126,9 @@ static void mpc92469ac_set(unsigned screen, unsigned int fout)
}
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
-static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
+static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
{
unsigned long long n;
unsigned long long mint;
@@ -164,11 +139,11 @@ static unsigned int ics8n3qv01_get_fout_calc(unsigned screen, unsigned index)
if (index > 3)
return 0;
- reg_a = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0 + index);
- reg_b = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 4 + index);
- reg_c = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 8 + index);
- reg_d = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 12 + index);
- reg_f = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20 + index);
+ reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
+ reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
+ reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
+ reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
+ reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
@@ -216,7 +191,7 @@ static void ics8n3qv01_calc_parameters(unsigned int fout,
*_n = n;
}
-static void ics8n3qv01_set(unsigned screen, unsigned int fout)
+static void ics8n3qv01_set(unsigned int fout)
{
unsigned int n;
unsigned int mint;
@@ -226,7 +201,7 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
long long off_ppm;
u8 reg0, reg4, reg8, reg12, reg18, reg20;
- fout_calc = ics8n3qv01_get_fout_calc(screen, 1);
+ fout_calc = ics8n3qv01_get_fout_calc(1);
off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
/ ICS8N3QV01_F_DEFAULT_1;
printf(" PLL is off by %lld ppm\n", off_ppm);
@@ -234,28 +209,28 @@ static void ics8n3qv01_set(unsigned screen, unsigned int fout)
/ ICS8N3QV01_F_DEFAULT_1;
ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
- reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+ reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
reg0 |= (mint & 0x1f) << 1;
reg0 |= (mfrac >> 17) & 0x01;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
reg4 = mfrac >> 9;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
reg8 = mfrac >> 1;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
reg12 = mfrac << 7;
reg12 |= n & 0x7f;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
- reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+ reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
reg18 |= 0x20;
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
- reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+ reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
reg20 |= mint & (1 << 5);
- fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
+ i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
}
#endif
@@ -315,9 +290,9 @@ int osd_probe(unsigned screen)
u16 version;
u16 features;
u8 value;
-#ifdef CONFIG_SYS_CH7301
int old_bus = i2c_get_bus_num();
-#endif
+ bool pixclock_present = false;
+ bool output_driver_present = false;
FPGA_GET_REG(0, osd.version, &version);
FPGA_GET_REG(0, osd.features, &features);
@@ -332,50 +307,76 @@ int osd_probe(unsigned screen)
printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
screen, version/100, version%100, base_width, base_height);
-#ifdef CONFIG_SYS_CH7301
- i2c_set_bus_num(ch7301_i2c[screen]);
- value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
- if (value != 0x17) {
- printf(" Probing CH7301 failed, DID %02x\n", value);
- i2c_set_bus_num(old_bus);
- return -1;
- }
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
- i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
- i2c_set_bus_num(old_bus);
-#endif
+ /* setup pixclock */
#ifdef CONFIG_SYS_MPC92469AC
+ pixclock_present = true;
mpc92469ac_set(screen, PIXCLK_640_480_60);
#endif
-#ifdef CONFIG_SYS_ICS8N3QV01
- ics8n3qv01_set(screen, PIXCLK_640_480_60);
+#ifdef CONFIG_SYS_ICS8N3QV01_I2C
+ i2c_set_bus_num(ics8n3qv01_i2c[screen]);
+ if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
+ ics8n3qv01_set(PIXCLK_640_480_60);
+ pixclock_present = true;
+ }
#endif
-#ifdef CONFIG_SYS_SIL1178
- value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
- if (value != 0x06) {
- printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
- return -1;
+ if (!pixclock_present)
+ printf(" no pixelclock found\n");
+
+ /* setup output driver */
+
+#ifdef CONFIG_SYS_CH7301_I2C
+ i2c_set_bus_num(ch7301_i2c[screen]);
+ if (!i2c_probe(CH7301_I2C_ADDR)) {
+ value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
+ if (value == 0x17) {
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
+ i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+ output_driver_present = true;
+ }
+ }
+#endif
+
+#ifdef CONFIG_SYS_SIL1178_I2C
+ i2c_set_bus_num(sil1178_i2c[screen]);
+ if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
+ value = i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02);
+ if (value == 0x06) {
+ /*
+ * magic initialization sequence,
+ * adapted from datasheet
+ */
+ i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+ i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+ output_driver_present = true;
+ }
}
- /* magic initialization sequence adapted from datasheet */
- fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
- fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
#endif
- FPGA_SET_REG(screen, videocontrol, 0x0002);
+#ifdef CONFIG_SYS_DP501_I2C
+ i2c_set_bus_num(dp501_i2c[screen]);
+ if (!i2c_probe(DP501_I2C_ADDR)) {
+ dp501_powerup(DP501_I2C_ADDR);
+ output_driver_present = true;
+ }
+#endif
+
+ if (!output_driver_present)
+ printf(" no output driver found\n");
+
FPGA_SET_REG(screen, osd.control, 0x0049);
FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
@@ -385,6 +386,8 @@ int osd_probe(unsigned screen)
if (screen > max_osd_screen)
max_osd_screen = screen;
+ i2c_set_bus_num(old_bus);
+
return 0;
}
diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c
index 3fca3c5..70eff91 100644
--- a/board/gdsys/p1022/controlcenterd-id.c
+++ b/board/gdsys/p1022/controlcenterd-id.c
@@ -30,7 +30,7 @@
#include <i2c.h>
#include <mmc.h>
#include <tpm.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
#include <pca9698.h>
@@ -86,6 +86,11 @@ enum {
ESDHC_BOOT_IMAGE_ENTRY_OFS = 0x60,
};
+enum {
+ I2C_SOC_0 = 0,
+ I2C_SOC_1 = 1,
+};
+
struct key_program {
uint32_t magic;
uint32_t code_crc;
@@ -1156,7 +1161,7 @@ static void ccdm_hang(void)
int j;
#endif
- I2C_SET_BUS(0);
+ I2C_SET_BUS(I2C_SOC_0);
pca9698_direction_output(0x22, 0, 0); /* Finder */
pca9698_direction_output(0x22, 4, 0); /* Status */
@@ -1189,8 +1194,8 @@ int startup_ccdm_id_module(void)
int result = 0;
unsigned int orig_i2c_bus;
- orig_i2c_bus = I2C_GET_BUS();
- I2C_SET_BUS(1);
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(I2C_SOC_1);
/* goto end; */
@@ -1216,7 +1221,7 @@ int startup_ccdm_id_module(void)
failure:
result = 1;
end:
- I2C_SET_BUS(orig_i2c_bus);
+ i2c_set_bus_num(orig_i2c_bus);
if (result)
ccdm_hang();
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index 8ccd9ce..f76d968 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -221,11 +221,7 @@ void hw_watchdog_reset(void)
#ifdef CONFIG_TRAILBLAZER
int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int rcode = 0;
-
- if (run_command(getenv("bootcmd"), flag) < 0)
- rcode = 1;
- return rcode;
+ return run_command(getenv("bootcmd"), flag);
}
int board_early_init_r(void)
@@ -386,9 +382,9 @@ static void hydra_initialize(void)
fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM);
- versions = readl(fpga->versions);
- fpga_version = readl(fpga->fpga_version);
- fpga_features = readl(fpga->fpga_features);
+ versions = readl(&fpga->versions);
+ fpga_version = readl(&fpga->fpga_version);
+ fpga_features = readl(&fpga->fpga_features);
hardware_version = versions & 0xf;
feature_uart_channels = (fpga_features >> 6) & 0x1f;
diff --git a/board/gdsys/p1022/sdhc_boot.c b/board/gdsys/p1022/sdhc_boot.c
index e432318..fd0e910 100644
--- a/board/gdsys/p1022/sdhc_boot.c
+++ b/board/gdsys/p1022/sdhc_boot.c
@@ -32,7 +32,7 @@
#define ESDHC_BOOT_IMAGE_SIZE 0x48
#define ESDHC_BOOT_IMAGE_ADDR 0x50
-int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr)
+int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
{
u8 *tmp_buf;
u32 blklen, code_offset, code_len, n;
generated by cgit v1.1 at 2024-11-06 10:09:26 +0000