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-rw-r--r--board/gdsys/gdppc440etx/gdppc440etx.c63
-rw-r--r--board/gdsys/intip/intip.c37
2 files changed, 0 insertions, 100 deletions
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
index 92f5d82..b93a420 100644
--- a/board/gdsys/gdppc440etx/gdppc440etx.c
+++ b/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -217,69 +217,6 @@ int pci_pre_init(struct pci_controller *hose)
#endif /* defined(CONFIG_PCI) */
/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*
- * Set up Direct MMIO registers
- */
-
- /*
- * PowerPC440 EP PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF
- * ==> PCI address 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIL0_PMM0MA, 0x00000000); /* disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIL0_PMM0PCIHA, 0x00000000);
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIL0_PMM1PCIHA, 0x00000000);
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001);
- out32r(PCIL0_PTM1LA, 0);
- out32r(PCIL0_PTM2MS, 0);
- out32r(PCIL0_PTM2LA, 0);
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*
* pci_master_init
*
*/
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index 49d2451..23a10c4 100644
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -141,43 +141,6 @@ int checkboard(void)
return 0;
}
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*
- * Disable everything
- */
- out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
- out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options to not support sizes such as 128/256 MB.
- */
- out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out_le32((void *)PCIL0_PIM0LAH, 0);
- out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out_le32((void *)PCIL0_BAR0, 0);
-
- /*
- * Program the board's subsystem id/vendor id
- */
- out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
int board_early_init_r(void)
{
/*