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path: root/board/gdsys/405ep/iocon.c
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Diffstat (limited to 'board/gdsys/405ep/iocon.c')
-rw-r--r--board/gdsys/405ep/iocon.c44
1 files changed, 36 insertions, 8 deletions
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 9f84fb1..f6502b3 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -44,6 +44,8 @@ enum {
HWVER_120 = 3,
HWVER_200 = 4,
HWVER_210 = 5,
+ HWVER_220 = 6,
+ HWVER_230 = 7,
};
enum {
@@ -74,6 +76,11 @@ enum {
};
enum {
+ CARRIER_SPEED_1G = 0,
+ CARRIER_SPEED_2_5G = 1,
+};
+
+enum {
MCFPGA_DONE = 1 << 0,
MCFPGA_INIT_N = 1 << 1,
MCFPGA_PROGRAM_N = 1 << 2,
@@ -168,8 +175,10 @@ static void print_fpga_info(unsigned int fpga)
unsigned feature_audio;
unsigned feature_sysclock;
unsigned feature_ramconfig;
+ unsigned feature_carrier_speed;
unsigned feature_carriers;
unsigned feature_video_channels;
+
int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
FPGA_GET_REG(0, versions, &versions);
@@ -182,6 +191,7 @@ static void print_fpga_info(unsigned int fpga)
feature_audio = (fpga_features & 0x0600) >> 9;
feature_sysclock = (fpga_features & 0x0180) >> 7;
feature_ramconfig = (fpga_features & 0x0060) >> 5;
+ feature_carrier_speed = fpga_features & (1<<4);
feature_carriers = (fpga_features & 0x000c) >> 2;
feature_video_channels = fpga_features & 0x0003;
@@ -237,6 +247,14 @@ static void print_fpga_info(unsigned int fpga)
printf(" HW-Ver 2.10,");
break;
+ case HWVER_220:
+ printf(" HW-Ver 2.20,");
+ break;
+
+ case HWVER_230:
+ printf(" HW-Ver 2.30,");
+ break;
+
default:
printf(" HW-Ver %d(not supported),",
hardware_version);
@@ -334,7 +352,8 @@ static void print_fpga_info(unsigned int fpga)
break;
}
- printf(", %d carrier(s)", feature_carriers);
+ printf(", %d carrier(s) %s", feature_carriers,
+ feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
printf(", %d video channel(s)\n", feature_video_channels);
}
@@ -345,6 +364,10 @@ int last_stage_init(void)
unsigned int k;
unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
+ u16 fpga_features;
+ int feature_carrier_speed = fpga_features & (1<<4);
+
+ FPGA_GET_REG(0, fpga_features, &fpga_features);
print_fpga_info(0);
osd_probe(0);
@@ -366,7 +389,7 @@ int last_stage_init(void)
}
}
- if (!legacy) {
+ if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) {
miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
bb_miiphy_write);
if (!verify_88e1518(bb_miiphy_buses[0].name, 0)) {
@@ -389,14 +412,19 @@ int last_stage_init(void)
mclink_fpgacount = slaves;
for (k = 1; k <= slaves; ++k) {
+ FPGA_GET_REG(k, fpga_features, &fpga_features);
+ feature_carrier_speed = fpga_features & (1<<4);
+
print_fpga_info(k);
osd_probe(k);
- miiphy_register(bb_miiphy_buses[k].name,
- bb_miiphy_read, bb_miiphy_write);
- if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) {
- printf("Fixup 88e1518 erratum on %s\n",
- bb_miiphy_buses[k].name);
- setup_88e1518(bb_miiphy_buses[k].name, 0);
+ if (feature_carrier_speed == CARRIER_SPEED_1G) {
+ miiphy_register(bb_miiphy_buses[k].name,
+ bb_miiphy_read, bb_miiphy_write);
+ if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) {
+ printf("Fixup 88e1518 erratum on %s\n",
+ bb_miiphy_buses[k].name);
+ setup_88e1518(bb_miiphy_buses[k].name, 0);
+ }
}
}