1 files changed, 64 insertions, 15 deletions

diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index db1ea7f..070dcbb 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -27,10 +27,16 @@
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
 
+#include <dtt.h>
 #include <miiphy.h>
 
+#include "405ep.h"
 #include <gdsys_fpga.h>
 
+#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
+#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
+#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
+
 #define PHYREG_CONTROL				0
 #define PHYREG_PAGE_ADDRESS			22
 #define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1	16
@@ -47,6 +53,14 @@ enum {
 	HWVER_122 = 3,
 };
 
+int misc_init_r(void)
+{
+	/* startup fans */
+	dtt_init();
+
+	return 0;
+}
+
 int configure_gbit_phy(unsigned char addr)
 {
 	unsigned short value;
@@ -87,9 +101,23 @@ err_out:
  */
 int checkboard(void)
 {
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+	char *s = getenv("serial#");
+
+	puts("Board: CATCenter Io");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	return 0;
+}
+
+static void print_fpga_info(void)
+{
+	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
 	u16 versions = in_le16(&fpga->versions);
 	u16 fpga_version = in_le16(&fpga->fpga_version);
 	u16 fpga_features = in_le16(&fpga->fpga_features);
@@ -103,15 +131,7 @@ int checkboard(void)
 	feature_channels = fpga_features & 0x007f;
 	feature_expansion = fpga_features & (1<<15);
 
-	printf("Board: ");
-
-	printf("CATCenter Io");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	puts("\n       ");
+	puts("FPGA:  ");
 
 	switch (unit_type) {
 	case UNITTYPE_CCD_SWITCH:
@@ -152,8 +172,6 @@ int checkboard(void)
 	printf(" %d channel(s)", feature_channels);
 
 	printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
-
-	return 0;
 }
 
 /*
@@ -161,9 +179,11 @@ int checkboard(void)
  */
 int last_stage_init(void)
 {
-	ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
+	struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
 	unsigned int k;
 
+	print_fpga_info();
+
 	miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
 		bb_miiphy_read, bb_miiphy_write);
 
@@ -175,3 +195,32 @@ int last_stage_init(void)
 
 	return 0;
 }
+
+void gd405ep_init(void)
+{
+}
+
+void gd405ep_set_fpga_reset(unsigned state)
+{
+	if (state) {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
+	} else {
+		out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
+		out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
+	}
+}
+
+void gd405ep_setup_hw(void)
+{
+	/*
+	 * set "startup-finished"-gpios
+	 */
+	gpio_write_bit(21, 0);
+	gpio_write_bit(22, 1);
+}
+
+int gd405ep_get_fpga_done(unsigned fpga)
+{
+	return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
+}