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-rw-r--r--board/freescale/mx35_3stack/Makefile1
-rw-r--r--board/freescale/mx35_3stack/flash_header.S108
-rw-r--r--board/freescale/mx35_3stack/mx35_3stack.c123
-rw-r--r--board/freescale/mx35_3stack/u-boot.lds2
-rw-r--r--board/freescale/mx51_3stack/mx51_3stack.c79
-rw-r--r--board/freescale/mx51_3stack/u-boot.lds1
6 files changed, 314 insertions, 0 deletions
diff --git a/board/freescale/mx35_3stack/Makefile b/board/freescale/mx35_3stack/Makefile
index 4c38a8b..d310b82 100644
--- a/board/freescale/mx35_3stack/Makefile
+++ b/board/freescale/mx35_3stack/Makefile
@@ -25,6 +25,7 @@ LIB = $(obj)lib$(BOARD).a
COBJS := mx35_3stack.o
SOBJS := lowlevel_init.o
+SOBJS += flash_header.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/mx35_3stack/flash_header.S b/board/freescale/mx35_3stack/flash_header.S
new file mode 100644
index 0000000..6786e8d
--- /dev/null
+++ b/board/freescale/mx35_3stack/flash_header.S
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx35.h>
+#include "board-mx35_3stack.h"
+
+#ifdef CONFIG_FLASH_HEADER
+#ifndef FHEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+
+/* Flash header setup */
+#define DCDGEN(i,type, addr, data) \
+dcd_##i: ;\
+ .long type ;\
+ .long addr ;\
+ .long data
+
+#define GEN_FHEADERADDR(x) (x)
+
+.section ".text.flasheader", "x"
+ b _start
+ .org FHEADER_OFFSET
+app_code_jump_v: .long GEN_FHEADERADDR(_start)
+app_code_barker: .long 0xB1
+app_code_csf: .long 0
+hwcfg_ptr_ptr: .long GEN_FHEADERADDR(hwcfg_ptr)
+super_root_key: .long 0
+hwcfg_ptr: .long GEN_FHEADERADDR(dcd_data)
+app_dest_ptr: .long TEXT_BASE
+dcd_data: .long 0xB17219E9
+#ifdef MEMORY_MDDR_ENABLE
+ .long (dcd_data_end - dcd_data - 8)
+
+//WEIM config-CS5 init
+DCDGEN(1, 4, 0xB8002054, 0x444a4541)
+DCDGEN(1_1, 4, 0xB8002050, 0x0000dcf6)
+DCDGEN(1_2, 4, 0xB8002058, 0x44443302)
+//MDDR init
+//enable mDDR
+DCDGEN(2, 4, 0xB8001010, 0x00000004)
+//reset delay time
+DCDGEN(3, 4, 0xB8001010, 0x0000000C)
+DCDGEN(4, 4, 0xB800100C, 0x007ffc3f)
+DCDGEN(5, 4, 0xB800100C, 0x007ffc3f)
+DCDGEN(6, 4, 0xB8001004, 0x007ffc3f)
+DCDGEN(7, 4, 0xB8001000, 0x92220000)
+DCDGEN(8, 1, 0x80000400, 0xda)
+DCDGEN(9, 4, 0xB8001000, 0xA2220000)
+DCDGEN(10, 4, 0x80000000, 0x87654321)
+DCDGEN(11, 4, 0x80000000, 0x87654321)
+DCDGEN(12, 4, 0xB8001000, 0xB2220000)
+DCDGEN(13, 1, 0x80000033, 0xda)
+DCDGEN(14, 1, 0x82000000, 0xda)
+DCDGEN(15, 4, 0xB8001000, 0x82226080)
+DCDGEN(16, 4, 0xB8001010, 0x00000004)
+DCDGEN(17, 4, 0xB8001008, 0x00002000)
+
+#else
+ .long 240
+
+//WEIM config-CS5 init
+DCDGEN(1, 4, 0xB8002050, 0x0000d843)
+DCDGEN(1_1, 4, 0xB8002054, 0x22252521)
+DCDGEN(1_2, 4, 0xB8002058, 0x22220a00)
+
+//DDR2 init
+DCDGEN(2, 4, 0xB8001010, 0x00000304)
+DCDGEN(3, 4, 0xB8001010, 0x0000030C)
+DCDGEN(4, 4, 0xB8001004, 0x007ffc3f)
+DCDGEN(5, 4, 0xB8001000, 0x92220000)
+DCDGEN(6, 4, 0x80000400, 0x12345678)
+DCDGEN(7, 4, 0xB8001000, 0xA2220000)
+DCDGEN(8, 4, 0x80000000, 0x87654321)
+DCDGEN(9, 4, 0x80000000, 0x87654321)
+DCDGEN(10, 4, 0xB8001000, 0xB2220000)
+DCDGEN(11, 1, 0x80000233, 0xda)
+DCDGEN(12, 1, 0x82000780, 0xda)
+DCDGEN(13, 1, 0x82000400, 0xda)
+DCDGEN(14, 4, 0xB8001000, 0x82226080)
+DCDGEN(15, 4, 0xB8001004, 0x007ffc3f)
+DCDGEN(16, 4, 0xB800100C, 0x007ffc3f)
+DCDGEN(17, 4, 0xB8001010, 0x00000304)
+DCDGEN(18, 4, 0xB8001008, 0x00002000)
+
+#endif
+dcd_data_end:
+
+//CARD_FLASH_CFG_PARMS_T---length
+card_cfg: .long 0x100000
+#endif
diff --git a/board/freescale/mx35_3stack/mx35_3stack.c b/board/freescale/mx35_3stack/mx35_3stack.c
index 41163f4..f7fb96a 100644
--- a/board/freescale/mx35_3stack/mx35_3stack.c
+++ b/board/freescale/mx35_3stack/mx35_3stack.c
@@ -29,8 +29,13 @@
#include <asm/arch/mx35_pins.h>
#include <asm/arch/iomux.h>
#include <i2c.h>
+#include <linux/types.h>
+#ifdef CONFIG_MMC
+#include <asm/arch/sdhc.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
+volatile u32 *esdhc_base_pointer;
static u32 system_rev;
@@ -279,3 +284,121 @@ int board_eth_init(bd_t *bis)
#endif
return rc;
}
+
+#ifdef CONFIG_FSL_MMC
+
+int sdhc_init(void)
+{
+ u32 interface_esdhc = 0;
+ u32 pad_val = 0;
+
+ interface_esdhc = (readl(IIM_BASE_ADDR + 0x80c)) & (0x000000C0) >> 6;
+
+ if (!is_soc_rev(CHIP_REV_1_0)) {
+ pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
+ PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
+
+ switch (interface_esdhc) {
+ case 0:
+ debug("TO1 ESDHC1\n");
+
+ esdhc_base_pointer = \
+ (volatile u32 *)MMC_SDHC1_BASE_ADDR;
+
+ mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val);
+ break;
+ case 1:
+ debug("TO1 ESDHC2\n");
+
+ esdhc_base_pointer = \
+ (volatile u32 *)MMC_SDHC2_BASE_ADDR;
+
+ mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val);
+ break;
+ case 2:
+ debug("TO1 ESDHC3\n");
+
+ esdhc_base_pointer = \
+ (volatile u32 *)MMC_SDHC3_BASE_ADDR;
+
+ printf("TO1 ESDHC3 not supported!");
+ break;
+ default:
+ break;
+ }
+ } else if (!is_soc_rev(CHIP_REV_2_0)) {
+ /* IOMUX PROGRAMMING */
+ switch (interface_esdhc) {
+ case 0:
+ debug("TO2 ESDHC1\n");
+
+ esdhc_base_pointer = \
+ (volatile u32 *)MMC_SDHC1_BASE_ADDR;
+
+ pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
+ PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
+ mxc_request_iomux(MX35_PIN_SD1_CLK,
+ MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX35_PIN_SD1_CLK, pad_val);
+
+ pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_HIGH |
+ PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
+ mxc_request_iomux(MX35_PIN_SD1_CMD,
+ MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX35_PIN_SD1_CMD, pad_val);
+ mxc_request_iomux(MX35_PIN_SD1_DATA0,
+ MUX_CONFIG_FUNC);
+ mxc_iomux_set_pad(MX35_PIN_SD1_DATA0, pad_val);
+ mxc_request_iomux(MX35_PIN_SD1_DATA3,
+ MUX_CONFIG_FUNC);
+ mxc_iomux_set_pad(MX35_PIN_SD1_DATA3, pad_val);
+
+ break;
+ case 1:
+ debug("TO2 ESDHC2\n");
+
+ esdhc_base_pointer = \
+ (volatile u32 *)MMC_SDHC2_BASE_ADDR;
+
+ mxc_request_iomux(MX35_PIN_SD2_CLK,
+ MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_SD2_CMD,
+ MUX_CONFIG_FUNC | MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_SD2_DATA0,
+ MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_SD2_DATA3,
+ MUX_CONFIG_FUNC);
+
+ pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
+ PAD_CTL_47K_PU | PAD_CTL_SRE_FAST;
+ mxc_iomux_set_pad(MX35_PIN_SD2_CLK, pad_val);
+
+ pad_val = PAD_CTL_PUE_PUD | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_HYS_SCHMITZ | PAD_CTL_DRV_MAX |
+ PAD_CTL_100K_PU | PAD_CTL_SRE_FAST;
+ mxc_iomux_set_pad(MX35_PIN_SD2_CMD, pad_val);
+ mxc_iomux_set_pad(MX35_PIN_SD2_DATA0, pad_val);
+ mxc_iomux_set_pad(MX35_PIN_SD2_DATA3, pad_val);
+
+ break;
+ case 2:
+ debug("TO2 ESDHC3\n");
+
+ esdhc_base_pointer = \
+ (volatile u32 *)MMC_SDHC3_BASE_ADDR;
+
+ printf("TO2 ESDHC3 not supported!");
+ break;
+ default:
+ break;
+ }
+ }
+
+ return 0;
+}
+
+#endif
diff --git a/board/freescale/mx35_3stack/u-boot.lds b/board/freescale/mx35_3stack/u-boot.lds
index 1b343be..c0156b5 100644
--- a/board/freescale/mx35_3stack/u-boot.lds
+++ b/board/freescale/mx35_3stack/u-boot.lds
@@ -38,6 +38,7 @@ SECTIONS
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
+ board/freescale/mx35_3stack/flash_header.o (.text.flasheader)
*(.text.head) /*arm startup code*/
*(.text.init) /*platform lowlevel initial code*/
*(.text.load) /*load bootloader*/
@@ -47,6 +48,7 @@ SECTIONS
lib_arm/libarm.a (.text)
net/libnet.a (.text)
drivers/mtd/libmtd.a (.text)
+ drivers/mmc/libmmc.a (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o(.text)
diff --git a/board/freescale/mx51_3stack/mx51_3stack.c b/board/freescale/mx51_3stack/mx51_3stack.c
index c7f93aa..9ddee40 100644
--- a/board/freescale/mx51_3stack/mx51_3stack.c
+++ b/board/freescale/mx51_3stack/mx51_3stack.c
@@ -35,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
static u32 system_rev;
u32 mx51_io_base_addr;
+volatile u32 *esdhc_base_pointer;
u32 get_board_rev(void)
{
@@ -209,3 +210,81 @@ int board_eth_init(bd_t *bis)
return rc;
}
#endif
+
+#ifdef CONFIG_FSL_MMC
+
+int sdhc_init(void)
+{
+ u32 interface_esdhc = 0;
+ u32 pad_val = 0;
+ s32 status = 0;
+
+ interface_esdhc = (readl(SRC_BASE_ADDR + 0x4) & (0x00180000)) >> 19;
+
+ switch (interface_esdhc) {
+ case 0:
+
+ esdhc_base_pointer = (volatile u32 *)MMC_SDHC1_BASE_ADDR;
+
+ mxc_request_iomux(MX51_PIN_SD1_CMD,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_request_iomux(MX51_PIN_SD1_CLK,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+
+ mxc_request_iomux(MX51_PIN_SD1_DATA0,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_request_iomux(MX51_PIN_SD1_DATA1,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_request_iomux(MX51_PIN_SD1_DATA2,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_request_iomux(MX51_PIN_SD1_DATA3,
+ IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
+ PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
+ PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
+ PAD_CTL_PUE_PULL |
+ PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ break;
+ case 1:
+ status = 1;
+ break;
+ case 2:
+ status = 1;
+ break;
+ case 3:
+ status = 1;
+ break;
+ default:
+ status = 1;
+ break;
+ }
+
+ return status = 1;
+}
+
+#endif
diff --git a/board/freescale/mx51_3stack/u-boot.lds b/board/freescale/mx51_3stack/u-boot.lds
index 1cf3c3d..8671fff 100644
--- a/board/freescale/mx51_3stack/u-boot.lds
+++ b/board/freescale/mx51_3stack/u-boot.lds
@@ -44,6 +44,7 @@ SECTIONS
lib_arm/libarm.a (.text)
net/libnet.a (.text)
drivers/mtd/libmtd.a (.text)
+ drivers/mmc/libmmc.a (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o(.text)
generated by cgit v1.1 at 2024-11-21 23:07:32 +0000