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-rw-r--r--board/freescale/common/pixis.c28
-rw-r--r--board/freescale/common/sys_eeprom.c23
-rw-r--r--board/freescale/mpc5121ads/Makefile53
-rw-r--r--board/freescale/mpc5121ads/README7
-rw-r--r--board/freescale/mpc5121ads/config.mk23
-rw-r--r--board/freescale/mpc5121ads/mpc5121ads.c366
-rw-r--r--board/freescale/mpc8349emds/mpc8349emds.c2
-rw-r--r--board/freescale/mpc8569mds/bcsr.c19
-rw-r--r--board/freescale/mpc8569mds/bcsr.h2
-rw-r--r--board/freescale/mpc8569mds/mpc8569mds.c126
-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c4
-rw-r--r--board/freescale/mx31ads/config.mk2
-rw-r--r--board/freescale/p2020ds/Makefile54
-rw-r--r--board/freescale/p2020ds/config.mk32
-rw-r--r--board/freescale/p2020ds/ddr.c130
-rw-r--r--board/freescale/p2020ds/law.c42
-rw-r--r--board/freescale/p2020ds/p2020ds.c634
-rw-r--r--board/freescale/p2020ds/tlb.c95
-rw-r--r--board/freescale/p2020ds/u-boot.lds143
19 files changed, 1761 insertions, 24 deletions
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index eb76d93..4851f06 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -279,9 +279,10 @@ int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
}
U_BOOT_CMD(
- diswd, 1, 0, pixis_disable_watchdog_cmd,
- "Disable watchdog timer",
- NULL);
+ diswd, 1, 0, pixis_disable_watchdog_cmd,
+ "Disable watchdog timer",
+ ""
+);
#ifdef CONFIG_PIXIS_SGMII_CMD
int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -343,14 +344,15 @@ int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
- pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
- "pixis_set_sgmii"
- " - Enable or disable SGMII mode for a given TSEC \n",
- "\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
- " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
- " on - enables SGMII\n"
- " off - disables SGMII\n"
- " switch - use switch settings\n");
+ pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
+ "pixis_set_sgmii"
+ " - Enable or disable SGMII mode for a given TSEC \n",
+ "\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
+ " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
+ " on - enables SGMII\n"
+ " off - disables SGMII\n"
+ " switch - use switch settings"
+);
#endif
/*
@@ -544,5 +546,5 @@ U_BOOT_CMD(
" pixis_reset [altbank]\n"
" pixis_reset altbank wd\n"
" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
- " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
- );
+ " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
+);
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 988cb94..ae5304a 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2006, 2008 Freescale Semiconductor
+ * Copyright 2006, 2008-2009 Freescale Semiconductor
* York Sun (yorksun@freescale.com)
* Haiying Wang (haiying.wang@freescale.com)
* Timur Tabi (timur@freescale.com)
@@ -34,6 +34,8 @@
#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or CONFIG_SYS_I2C_EEPROM_NXID"
#endif
+#define MAX_NUM_PORTS 8 /* This value must be 8 as defined in doc */
+
/**
* static eeprom: EEPROM layout for CCID or NXID formats
*
@@ -50,7 +52,7 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 res_0[40]; /* 0x18 - 0x3f Reserved */
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
- u8 mac[8][6]; /* 0x42 - 0x71 MAC addresses */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
u32 crc; /* 0x72 CRC32 checksum */
#endif
#ifdef CONFIG_SYS_I2C_EEPROM_NXID
@@ -66,7 +68,7 @@ static struct __attribute__ ((__packed__)) eeprom {
u8 res_1[21]; /* 0x2b - 0x3f Reserved */
u8 mac_count; /* 0x40 Number of MAC addresses */
u8 mac_flag; /* 0x41 MAC table flags */
- u8 mac[8][6]; /* 0x42 - 0x71 MAC addresses */
+ u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - 0x71 MAC addresses */
u32 crc; /* 0x72 CRC32 checksum */
#endif
} e;
@@ -119,7 +121,8 @@ static void show_eeprom(void)
e.date[3] & 0x80 ? "PM" : "");
/* Show MAC addresses */
- for (i = 0; i < min(e.mac_count, 8); i++) {
+ for (i = 0; i < min(e.mac_count, MAX_NUM_PORTS); i++) {
+
u8 *p = e.mac[i];
printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
@@ -404,7 +407,17 @@ int mac_read_from_eeprom(void)
}
}
- for (i = 0; i < min(4, e.mac_count); i++) {
+ /* Check the number of MAC addresses which is limited to
+ * MAX_NUM_PORTS.
+ */
+ if (e.mac_count > MAX_NUM_PORTS) {
+ printf("Warning: The number of MAC addresses is greater"
+ " than %u, force it to %u.\n", MAX_NUM_PORTS,
+ MAX_NUM_PORTS);
+ e.mac_count = MAX_NUM_PORTS;
+ }
+
+ for (i = 0; i < e.mac_count; i++) {
if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
char ethaddr[18];
diff --git a/board/freescale/mpc5121ads/Makefile b/board/freescale/mpc5121ads/Makefile
new file mode 100644
index 0000000..20fbf6e
--- /dev/null
+++ b/board/freescale/mpc5121ads/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+$(shell mkdir -p $(OBJTREE)/board/freescale/common)
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+
+COBJS := $(COBJS-y)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README
new file mode 100644
index 0000000..defcd6b
--- /dev/null
+++ b/board/freescale/mpc5121ads/README
@@ -0,0 +1,7 @@
+To configure for the current (Rev 3.x) ADS5121
+ make ads5121_config
+This will automatically include PCI, the Real Time CLock, add backup flash
+ability and set the correct frequency and memory configuration.
+
+To configure for the older Rev 2 ADS5121 type (this will not have PCI)
+ make ads5121_rev2_config
diff --git a/board/freescale/mpc5121ads/config.mk b/board/freescale/mpc5121ads/config.mk
new file mode 100644
index 0000000..14998f4
--- /dev/null
+++ b/board/freescale/mpc5121ads/config.mk
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2007 DENX Software Engineering
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFF00000
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
new file mode 100644
index 0000000..ec74fd3
--- /dev/null
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -0,0 +1,366 @@
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int mpc5121_diu_init(void);
+extern void ide_set_reset(int idereset);
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
+ CLOCK_SCCR1_DDR_EN | \
+ CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_LPC_EN | \
+ CLOCK_SCCR1_NFC_EN | \
+ CLOCK_SCCR1_PATA_EN | \
+ CLOCK_SCCR1_PCI_EN | \
+ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+ CLOCK_SCCR1_PSCFIFO_EN | \
+ CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
+ CLOCK_SCCR2_I2C_EN | \
+ CLOCK_SCCR2_MEM_EN | \
+ CLOCK_SCCR2_SPDIF_EN)
+
+#define CSAW_START(start) ((start) & 0xFFFF0000)
+#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
+
+long int fixed_sdram(void);
+void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
+
+/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
+extern int mpc5121_nfc_chip;
+
+/* Control chips select signal on MPC5121ADS board */
+void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
+{
+ unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
+ u8 v;
+
+ v = in_8(csreg);
+ v |= 0x0F;
+
+ if (chip >= 0) {
+ __mpc5121_nfc_select_chip(mtd, 0);
+ v &= ~(1 << mpc5121_nfc_chip);
+ } else {
+ __mpc5121_nfc_select_chip(mtd, -1);
+ }
+
+ out_8(csreg, v);
+}
+
+int board_early_init_f (void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 lpcaw, spridr;
+
+ /*
+ * Initialize Local Window for the CPLD registers access (CS2 selects
+ * the CPLD chip)
+ */
+ out_be32(&im->sysconf.lpcs2aw,
+ CSAW_START(CONFIG_SYS_CPLD_BASE) |
+ CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
+ );
+ out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+
+ /*
+ * According to MPC5121e RM, configuring local access windows should
+ * be followed by a dummy read of the config register that was
+ * modified last and an isync
+ */
+ lpcaw = in_be32(&im->sysconf.lpcs6aw);
+ __asm__ __volatile__ ("isync");
+
+ /*
+ * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
+ *
+ * Without this the flash identification routine fails, as it needs to issue
+ * write commands in order to establish the device ID.
+ */
+
+#ifdef CONFIG_ADS5121_REV2
+ out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
+#else
+ if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
+ out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
+ } else {
+ /* running from Backup flash */
+ out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
+ }
+#endif
+ /*
+ * Configure Flash Speed
+ */
+ out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+
+ spridr = in_be32(&im->sysconf.spridr);
+
+ if (SVR_MJREV (spridr) >= 2)
+ out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+ /*
+ * Enable clocks
+ */
+ out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+ out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+ setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+ u32 msize = 0;
+
+ msize = fixed_sdram ();
+
+ return msize;
+}
+
+/*
+ * fixed sdram init -- the board doesn't use memory modules that have serial presence
+ * detect or similar mechanism for discovery of the DRAM settings
+ */
+long int fixed_sdram (void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2 (msize);
+ u32 i;
+
+ /* Initialize IO Control */
+ out_be32 (&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+
+ /* Initialize DDR Local Window */
+ out_be32 (&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
+ out_be32 (&im->sysconf.ddrlaw.ar, msize_log2 - 1);
+
+ /*
+ * According to MPC5121e RM, configuring local access windows should
+ * be followed by a dummy read of the config register that was
+ * modified last and an isync
+ */
+ in_be32(&im->sysconf.ddrlaw.ar);
+ __asm__ __volatile__ ("isync");
+
+ /* Enable DDR */
+ out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
+
+ /* Initialize DDR Priority Manager */
+ out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
+ out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
+ out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
+ out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
+ out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
+ out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
+ out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
+ out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
+ out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
+ out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
+ out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
+ out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
+ out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
+ out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
+ out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
+ out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
+ out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
+ out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
+ out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
+ out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
+ out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
+ out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
+ out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
+
+ /* Initialize MDDRC */
+ out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
+ out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
+ out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
+ out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
+
+ /* Initialize DDR */
+ for (i = 0; i < 10; i++)
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+
+ /* Start MDDRC */
+ out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
+ out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
+
+ return msize;
+}
+
+int misc_init_r(void)
+{
+ u8 tmp_val;
+
+ /* Using this for DIU init before the driver in linux takes over
+ * Enable the TFP410 Encoder (I2C address 0x38)
+ */
+
+ i2c_set_bus_num(2);
+ tmp_val = 0xBF;
+ i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+ /* Verify if enabled */
+ tmp_val = 0;
+ i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+ debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+
+ tmp_val = 0x10;
+ i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+ /* Verify if enabled */
+ tmp_val = 0;
+ i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+ debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+
+#ifdef CONFIG_FSL_DIU_FB
+# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
+ mpc5121_diu_init();
+# endif
+#endif
+ return 0;
+}
+
+static iopin_t ioregs_init[] = {
+ /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+ {
+ offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* Set highest Slew on 9 PATA pins */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+ {
+ offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=SPDIF_TXCLK */
+ {
+ offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
+ {
+ offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIU CLK */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIU_HSYNC */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ }
+};
+
+static iopin_t rev2_silicon_pci_ioregs_init[] = {
+ /* FUNC0=PCI Sets next 54 to PCI pads */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+ }
+};
+
+int checkboard (void)
+{
+ ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
+ uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 spridr = in_be32(&im->sysconf.spridr);
+
+ printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
+ brd_rev, cpld_rev);
+
+ /* initialize function mux & slew rate IO inter alia on IO Pins */
+ iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+ if (SVR_MJREV (spridr) >= 2)
+ iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 06064d9..61d1249 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -38,7 +38,7 @@
int fixed_sdram(void);
void sdram_init(void);
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
void ddr_enable_ecc(unsigned int dram_size);
#endif
diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c
index f462597..a936edb 100644
--- a/board/freescale/mpc8569mds/bcsr.c
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -35,12 +35,29 @@ void disable_8569mds_flash_write()
clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
}
-void enable_8569mds_qe_mdio()
+void enable_8569mds_qe_uec()
{
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+ BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+ BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+ /* Set UCC1-4 working at RMII mode */
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+ BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+ BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+ BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+ BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
+#endif
}
void disable_8569mds_brd_eeprom_write_protect()
diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h
index 8efe9bd..e5d63c7 100644
--- a/board/freescale/mpc8569mds/bcsr.h
+++ b/board/freescale/mpc8569mds/bcsr.h
@@ -76,7 +76,7 @@
void enable_8569mds_flash_write(void);
void disable_8569mds_flash_write(void);
-void enable_8569mds_qe_mdio(void);
+void enable_8569mds_qe_uec(void);
void disable_8569mds_brd_eeprom_write_protect(void);
#endif /* __BCSR_H_ */
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 7e6cfb7..1e7526a 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -47,6 +47,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
/* QE_MUX_MDIO */
{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
/* UCC_1_RGMII */
{2, 11, 2, 0, 1}, /* CLK12 */
{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
@@ -77,6 +78,74 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
+ /* UCC_3_RGMII */
+ {2, 11, 2, 0, 1}, /* CLK12 */
+ {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
+ {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
+ {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
+ {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
+ {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
+ {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
+ {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
+ {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
+ {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
+ {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
+ {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
+ {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
+
+ /* UCC_4_RGMII */
+ {2, 16, 2, 0, 3}, /* CLK17 */
+ {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
+ {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
+ {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
+ {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
+ {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
+ {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
+ {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
+ {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
+ {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
+ {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
+ {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
+ {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
+
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+ /* UCC_1_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+ {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
+
+ /* UCC_2_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
+ {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
+ {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
+ {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
+ {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
+ {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
+
+ /* UCC_3_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
+ {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
+ {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
+ {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
+ {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
+ {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
+
+ /* UCC_4_RMII */
+ {2, 15, 2, 0, 1}, /* CLK16 */
+ {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
+ {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
+ {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
+ {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
+ {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
+ {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
+#endif
+
/* UART1 is muxed with QE PortF bit [9-12].*/
{5, 12, 2, 0, 3}, /* UART1_SIN */
{5, 9, 1, 0, 3}, /* UART1_SOUT */
@@ -98,7 +167,7 @@ int board_early_init_f (void)
enable_8569mds_flash_write();
#ifdef CONFIG_QE
- enable_8569mds_qe_mdio();
+ enable_8569mds_qe_uec();
#endif
#if CONFIG_SYS_I2C2_OFFSET
@@ -320,6 +389,61 @@ pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
+#if defined(CONFIG_SYS_UCC_RMII_MODE)
+ int nodeoff, off, err;
+ unsigned int val;
+ const u32 *ph;
+ const u32 *index;
+
+ /* fixup device tree for supporting rmii mode */
+ nodeoff = -1;
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
+ "ucc_geth")) >= 0) {
+ err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
+ "clk16");
+ if (err < 0) {
+ printf("WARNING: could not set tx-clock-name %s.\n",
+ fdt_strerror(err));
+ break;
+ }
+
+ err = fdt_setprop_string(blob, nodeoff, "phy-connection-type",
+ "rmii");
+ if (err < 0) {
+ printf("WARNING: could not set phy-connection-type "
+ "%s.\n", fdt_strerror(err));
+ break;
+ }
+
+ index = fdt_getprop(blob, nodeoff, "cell-index", 0);
+ if (index == NULL) {
+ printf("WARNING: could not get cell-index of ucc\n");
+ break;
+ }
+
+ ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
+ if (ph == NULL) {
+ printf("WARNING: could not get phy-handle of ucc\n");
+ break;
+ }
+
+ off = fdt_node_offset_by_phandle(blob, *ph);
+ if (off < 0) {
+ printf("WARNING: could not get phy node %s.\n",
+ fdt_strerror(err));
+ break;
+ }
+
+ val = 0x7 + *index; /* RMII phy address starts from 0x8 */
+
+ err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
+ if (err < 0) {
+ printf("WARNING: could not set reg for phy-handle "
+ "%s.\n", fdt_strerror(err));
+ break;
+ }
+ }
+#endif
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCIE1
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index 2b2d5d7..0ad878c 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -140,8 +140,8 @@ U_BOOT_CMD(
diufb, CONFIG_SYS_MAXARGS, 1, mpc8610diu_init_show_bmp,
"Init or Display BMP file",
"init\n - initialize DIU\n"
- "addr\n - display bmp at address 'addr'\n"
- );
+ "addr\n - display bmp at address 'addr'"
+);
#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
diff --git a/board/freescale/mx31ads/config.mk b/board/freescale/mx31ads/config.mk
index d34dc02..7ec0fe2 100644
--- a/board/freescale/mx31ads/config.mk
+++ b/board/freescale/mx31ads/config.mk
@@ -1 +1,3 @@
TEXT_BASE = 0x87f00000
+
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
diff --git a/board/freescale/p2020ds/Makefile b/board/freescale/p2020ds/Makefile
new file mode 100644
index 0000000..41032ac
--- /dev/null
+++ b/board/freescale/p2020ds/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p2020ds/config.mk b/board/freescale/p2020ds/config.mk
new file mode 100644
index 0000000..18bdc86
--- /dev/null
+++ b/board/freescale/p2020ds/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# p2020ds board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xeff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_P2020=1
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
new file mode 100644
index 0000000..b9c0cb2
--- /dev/null
+++ b/board/freescale/p2020ds/ddr.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0 && i == 0)
+ i2c_address = SPD_EEPROM_ADDRESS1;
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+typedef struct {
+ u32 datarate_mhz_low;
+ u32 datarate_mhz_high;
+ u32 n_ranks;
+ u32 clk_adjust;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2T;
+} board_specific_parameters_t;
+
+/* ranges for parameters:
+ * wr_data_delay = 0-6
+ * clk adjust = 0-8
+ * cpo 2-0x1E (30)
+ */
+
+
+/* XXX: these values need to be checked for all interleaving modes. */
+/* XXX: No reliable dual-rank 800 MHz setting has been found. It may
+ * seem reliable, but errors will appear when memory intensive
+ * program is run. */
+/* XXX: Single rank at 800 MHz is OK. */
+const board_specific_parameters_t board_specific_parameters[][20] = {
+ {
+ /* memory controller 0 */
+ /* lo| hi| num| clk| cpo|wrdata|2T */
+ /* mhz| mhz|ranks|adjst| | delay| */
+ { 0, 333, 2, 6, 7, 3, 0},
+ {334, 400, 2, 6, 9, 3, 0},
+ {401, 549, 2, 6, 11, 3, 0},
+ {550, 680, 2, 1, 10, 5, 0},
+ {681, 850, 2, 1, 12, 5, 1},
+ { 0, 333, 1, 6, 7, 3, 0},
+ {334, 400, 1, 6, 9, 3, 0},
+ {401, 549, 1, 6, 11, 3, 0},
+ {550, 680, 1, 1, 10, 5, 0},
+ {681, 850, 1, 1, 12, 5, 0}
+ },
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const board_specific_parameters_t *pbsp =
+ &(board_specific_parameters[ctrl_num][0]);
+ u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+ sizeof(board_specific_parameters[0][0]);
+ u32 i;
+ ulong ddr_freq;
+
+ /* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+ * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+ * there are two dimms in the controller, set odt_rd_cfg to 3 and
+ * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+ */
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (i&1) { /* odd CS */
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 0;
+ } else { /* even CS */
+ if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+ popts->cs_local_opts[i].odt_rd_cfg = 0;
+ popts->cs_local_opts[i].odt_wr_cfg = 4;
+ } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+ popts->cs_local_opts[i].odt_rd_cfg = 3;
+ popts->cs_local_opts[i].odt_wr_cfg = 3;
+ }
+ }
+ }
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ for (i = 0; i < num_params; i++) {
+ if (ddr_freq >= pbsp->datarate_mhz_low &&
+ ddr_freq <= pbsp->datarate_mhz_high &&
+ pdimm->n_ranks == pbsp->n_ranks) {
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay = pbsp->write_data_delay;
+ popts->twoT_en = pbsp->force_2T;
+ }
+ pbsp++;
+ }
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c
new file mode 100644
index 0000000..da297c5
--- /dev/null
+++ b/board/freescale/p2020ds/law.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
new file mode 100644
index 0000000..6b72d61
--- /dev/null
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -0,0 +1,634 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <asm/fsl_law.h>
+#include <asm/mp.h>
+
+#include "../common/pixis.h"
+#include "../common/sgmii_riser.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t fixed_sdram(void);
+
+int checkboard(void)
+{
+ puts("Board: P2020DS ");
+#ifdef CONFIG_PHYS_64BIT
+ puts("(36-bit addrmap) ");
+#endif
+ printf("Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
+ in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
+ in8(PIXIS_BASE + PIXIS_PVER));
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size = 0;
+
+ puts("Initializing....");
+
+#ifdef CONFIG_SPD_EEPROM
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fixed_sdram();
+
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+ dram_size,
+ LAW_TRGT_IF_DDR) < 0) {
+ printf("ERROR setting Local Access Windows for DDR\n");
+ return 0;
+ };
+#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram(void)
+{
+ volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+ uint d_init;
+
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+ ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+ ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
+ ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
+ ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
+ ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
+ ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
+
+ if (!strcmp("performance", getenv("perf_mode"))) {
+ /* Performance Mode Values */
+
+ ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
+ ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
+
+ asm("sync;isync");
+
+ udelay(500);
+
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
+ } else {
+ /* Stable Mode Values */
+
+ ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+
+ /* ECC will be assumed in stable mode */
+ ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+ ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+ ddr->err_sbe = CONFIG_SYS_DDR_SBE;
+
+ asm("sync;isync");
+
+ udelay(500);
+
+ ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+ }
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR - 1st controller: memory initializing\n");
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
+ udelay(1000);
+ debug("DDR: memory initialized\n\n");
+ asm("sync; isync");
+ udelay(500);
+#endif
+
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+
+#endif
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+int first_free_busno = 0;
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+ volatile ccsr_fsl_pci_t *pci;
+ struct pci_controller *hose;
+ int pcie_ep, pcie_configured;
+ struct pci_region *r;
+/* u32 temp32; */
+
+ debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+ devdisr, io_sel, host_agent);
+
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+ printf(" eTSEC2 is in sgmii mode.\n");
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ printf(" eTSEC3 is in sgmii mode.\n");
+
+#ifdef CONFIG_PCIE2
+ pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
+ hose = &pcie2_hose;
+ pcie_ep = (host_agent == 2) || (host_agent == 4) ||
+ (host_agent == 6) || (host_agent == 0);
+ pcie_configured = (io_sel == 0x2) || (io_sel == 0xe);
+ r = hose->regions;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
+ printf("\n PCIE2 connected to ULI as %s (base addr %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pci->pme_msg_det);
+ }
+ printf("\n");
+
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
+ /* outbound memory */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE2_MEM_BUS,
+ CONFIG_SYS_PCIE2_MEM_PHYS,
+ CONFIG_SYS_PCIE2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE2_IO_BUS,
+ CONFIG_SYS_PCIE2_IO_PHYS,
+ CONFIG_SYS_PCIE2_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = r - hose->regions;
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int)&pci->cfg_addr,
+ (int)&pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno = hose->last_busno+1;
+ printf(" PCIE2 on bus %02x - %02x\n",
+ hose->first_busno, hose->last_busno);
+
+ /*
+ * The workaround doesn't work on p2020 because the location
+ * we try and read isn't valid on p2020, fix this later
+ */
+#if 0
+ /*
+ * Activate ULI1575 legacy chip by performing a fake
+ * memory access. Needed to make ULI RTC work.
+ * Device 1d has the first on-board memory BAR.
+ */
+
+ pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
+ PCI_BASE_ADDRESS_1, &temp32);
+ if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
+ void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
+ temp32, 4, 0);
+ debug(" uli1575 read to %p\n", p);
+ in_be32(p);
+ }
+#endif
+ } else {
+ printf(" PCIE2: disabled\n");
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE3
+ pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
+ hose = &pcie3_hose;
+ pcie_ep = (host_agent == 0) || (host_agent == 3) ||
+ (host_agent == 5) || (host_agent == 6);
+ pcie_configured = (io_sel == 0x2) || (io_sel == 0x4);
+ r = hose->regions;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
+ printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pci->pme_msg_det);
+ }
+ printf("\n");
+
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
+ /* outbound memory */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE3_MEM_BUS,
+ CONFIG_SYS_PCIE3_MEM_PHYS,
+ CONFIG_SYS_PCIE3_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE3_IO_BUS,
+ CONFIG_SYS_PCIE3_IO_PHYS,
+ CONFIG_SYS_PCIE3_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = r - hose->regions;
+ hose->first_busno = first_free_busno;
+ pci_setup_indirect(hose, (int)&pci->cfg_addr,
+ (int)&pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno = hose->last_busno+1;
+ printf(" PCIE3 on bus %02x - %02x\n",
+ hose->first_busno, hose->last_busno);
+
+ } else {
+ printf(" PCIE3: disabled\n");
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+ pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
+ hose = &pcie1_hose;
+ pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5);
+ pcie_configured = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF);
+ r = hose->regions;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+ printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pci->pme_msg_det);
+ }
+ printf("\n");
+
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
+ /* outbound memory */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE1_MEM_BUS,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE1_IO_BUS,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = r - hose->regions;
+ hose->first_busno = first_free_busno;
+
+ pci_setup_indirect(hose, (int)&pci->cfg_addr,
+ (int)&pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno = hose->last_busno+1;
+ printf(" PCIE1 on bus %02x - %02x\n",
+ hose->first_busno, hose->last_busno);
+
+ } else {
+ printf(" PCIE1: disabled\n");
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+}
+#endif
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = 2;
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ return 0;
+}
+
+#ifdef CONFIG_GET_CLK_FROM_ICS307
+/* decode S[0-2] to Output Divider (OD) */
+static unsigned char ics307_S_to_OD[] = {
+ 10, 2, 8, 4, 5, 7, 3, 6
+};
+
+/* Calculate frequency being generated by ICS307-02 clock chip based upon
+ * the control bytes being programmed into it. */
+/* XXX: This function should probably go into a common library */
+static unsigned long
+ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
+{
+ const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
+ unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
+ unsigned long RDW = cw2 & 0x7F;
+ unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
+ unsigned long freq;
+
+ /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
+
+ /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
+ * cw1: V8 V7 V6 V5 V4 V3 V2 V1
+ * cw2: V0 R6 R5 R4 R3 R2 R1 R0
+ *
+ * R6:R0 = Reference Divider Word (RDW)
+ * V8:V0 = VCO Divider Word (VDW)
+ * S2:S0 = Output Divider Select (OD)
+ * F1:F0 = Function of CLK2 Output
+ * TTL = duty cycle
+ * C1:C0 = internal load capacitance for cyrstal
+ */
+
+ /* Adding 1 to get a "nicely" rounded number, but this needs
+ * more tweaking to get a "properly" rounded number. */
+
+ freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
+
+ debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
+ freq);
+ return freq;
+}
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ return gd->bus_clk;
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+ return gd->mem_clk;
+}
+
+unsigned long
+calculate_board_sys_clk(ulong dummy)
+{
+ ulong val;
+ val = ics307_clk_freq(
+ in8(PIXIS_BASE + PIXIS_VSYSCLK0),
+ in8(PIXIS_BASE + PIXIS_VSYSCLK1),
+ in8(PIXIS_BASE + PIXIS_VSYSCLK2));
+ debug("sysclk val = %lu\n", val);
+ return val;
+}
+
+unsigned long
+calculate_board_ddr_clk(ulong dummy)
+{
+ ulong val;
+ val = ics307_clk_freq(
+ in8(PIXIS_BASE + PIXIS_VDDRCLK0),
+ in8(PIXIS_BASE + PIXIS_VDDRCLK1),
+ in8(PIXIS_BASE + PIXIS_VDDRCLK2));
+ debug("ddrclk val = %lu\n", val);
+ return val;
+}
+#else
+unsigned long get_board_sys_clk(ulong dummy)
+{
+ u8 i;
+ ulong val = 0;
+
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33333333;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66666666;
+ break;
+ case 4:
+ val = 83333333;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 133333333;
+ break;
+ case 7:
+ val = 166666666;
+ break;
+ }
+
+ return val;
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+ u8 i;
+ ulong val = 0;
+
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ i &= 0x38;
+ i >>= 3;
+
+ switch (i) {
+ case 0:
+ val = 33333333;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66666666;
+ break;
+ case 4:
+ val = 83333333;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 133333333;
+ break;
+ case 7:
+ val = 166666666;
+ break;
+ }
+ return val;
+}
+#endif
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+ struct tsec_info_struct tsec_info[4];
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ int num = 0;
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+ tsec_info[num].flags |= TSEC_SGMII;
+ num++;
+#endif
+#ifdef CONFIG_TSEC3
+ SET_STD_TSEC_INFO(tsec_info[num], 3);
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ tsec_info[num].flags |= TSEC_SGMII;
+ num++;
+#endif
+
+ if (!num) {
+ printf("No TSECs initialized\n");
+
+ return 0;
+ }
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_init(tsec_info, num);
+#endif
+
+ tsec_eth_init(bis, tsec_info, num);
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCIE3
+ ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
+#endif
+#ifdef CONFIG_PCIE2
+ ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
+#endif
+#ifdef CONFIG_PCIE1
+ ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#endif
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+}
+#endif
+
+#ifdef CONFIG_MP
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c
new file mode 100644
index 0000000..b2e562a
--- /dev/null
+++ b/board/freescale/p2020ds/tlb.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_1M, 1),
+
+ /* W**G* - Flash/promjet, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* *I*G - NAND */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_1M, 1),
+
+ SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_4K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p2020ds/u-boot.lds b/board/freescale/p2020ds/u-boot.lds
new file mode 100644
index 0000000..d6e22a7
--- /dev/null
+++ b/board/freescale/p2020ds/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } :text
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ .bootpg ADDR(.text) + 0x7f000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ } :text = 0xffff
+
+ .resetvec ADDR(.text) + 0x7fffc :
+ {
+ *(.resetvec)
+ } :text = 0xffff
+
+ . = ADDR(.text) + 0x80000;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ _end = . ;
+ PROVIDE (end = .);
+}
generated by cgit v1.1 at 2024-12-11 18:15:54 +0000