diff options
Diffstat (limited to 'board/freescale')
29 files changed, 527 insertions, 880 deletions
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index 4851f06..7210512 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -39,7 +39,8 @@ static ulong strfractoint(uchar *strptr); */ void pixis_reset(void) { - out8(PIXIS_BASE + PIXIS_RST, 0); + u8 *pixis_base = (u8 *)PIXIS_BASE; + out_8(pixis_base + PIXIS_RST, 0); } @@ -49,6 +50,7 @@ void pixis_reset(void) int set_px_sysclk(ulong sysclk) { u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; + u8 *pixis_base = (u8 *)PIXIS_BASE; switch (sysclk) { case 33: @@ -107,10 +109,10 @@ int set_px_sysclk(ulong sysclk) vclkh = (sysclk_s << 5) | sysclk_r; vclkl = sysclk_v; - out8(PIXIS_BASE + PIXIS_VCLKH, vclkh); - out8(PIXIS_BASE + PIXIS_VCLKL, vclkl); + out_8(pixis_base + PIXIS_VCLKH, vclkh); + out_8(pixis_base + PIXIS_VCLKL, vclkl); - out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux); + out_8(pixis_base + PIXIS_AUX, sysclk_aux); return 1; } @@ -120,6 +122,7 @@ int set_px_mpxpll(ulong mpxpll) { u8 tmp; u8 val; + u8 *pixis_base = (u8 *)PIXIS_BASE; switch (mpxpll) { case 2: @@ -137,9 +140,9 @@ int set_px_mpxpll(ulong mpxpll) return 0; } - tmp = in8(PIXIS_BASE + PIXIS_VSPEED1); + tmp = in_8(pixis_base + PIXIS_VSPEED1); tmp = (tmp & 0xF0) | (val & 0x0F); - out8(PIXIS_BASE + PIXIS_VSPEED1, tmp); + out_8(pixis_base + PIXIS_VSPEED1, tmp); return 1; } @@ -149,6 +152,7 @@ int set_px_corepll(ulong corepll) { u8 tmp; u8 val; + u8 *pixis_base = (u8 *)PIXIS_BASE; switch ((int)corepll) { case 20: @@ -174,9 +178,9 @@ int set_px_corepll(ulong corepll) return 0; } - tmp = in8(PIXIS_BASE + PIXIS_VSPEED0); + tmp = in_8(pixis_base + PIXIS_VSPEED0); tmp = (tmp & 0xE0) | (val & 0x1F); - out8(PIXIS_BASE + PIXIS_VSPEED0, tmp); + out_8(pixis_base + PIXIS_VSPEED0, tmp); return 1; } @@ -184,27 +188,29 @@ int set_px_corepll(ulong corepll) void read_from_px_regs(int set) { + u8 *pixis_base = (u8 *)PIXIS_BASE; u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */ - u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0); + u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0); if (set) tmp = tmp | mask; else tmp = tmp & ~mask; - out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp); + out_8(pixis_base + PIXIS_VCFGEN0, tmp); } void read_from_px_regs_altbank(int set) { + u8 *pixis_base = (u8 *)PIXIS_BASE; u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */ - u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1); + u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1); if (set) tmp = tmp | mask; else tmp = tmp & ~mask; - out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp); + out_8(pixis_base + PIXIS_VCFGEN1, tmp); } #ifndef CONFIG_SYS_PIXIS_VBOOT_MASK @@ -214,50 +220,54 @@ void read_from_px_regs_altbank(int set) void clear_altbank(void) { u8 tmp; + u8 *pixis_base = (u8 *)PIXIS_BASE; - tmp = in8(PIXIS_BASE + PIXIS_VBOOT); + tmp = in_8(pixis_base + PIXIS_VBOOT); tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK; - out8(PIXIS_BASE + PIXIS_VBOOT, tmp); + out_8(pixis_base + PIXIS_VBOOT, tmp); } void set_altbank(void) { u8 tmp; + u8 *pixis_base = (u8 *)PIXIS_BASE; - tmp = in8(PIXIS_BASE + PIXIS_VBOOT); + tmp = in_8(pixis_base + PIXIS_VBOOT); tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK; - out8(PIXIS_BASE + PIXIS_VBOOT, tmp); + out_8(pixis_base + PIXIS_VBOOT, tmp); } void set_px_go(void) { u8 tmp; + u8 *pixis_base = (u8 *)PIXIS_BASE; - tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = in_8(pixis_base + PIXIS_VCTL); tmp = tmp & 0x1E; /* clear GO bit */ - out8(PIXIS_BASE + PIXIS_VCTL, tmp); + out_8(pixis_base + PIXIS_VCTL, tmp); - tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = in_8(pixis_base + PIXIS_VCTL); tmp = tmp | 0x01; /* set GO bit - start reset sequencer */ - out8(PIXIS_BASE + PIXIS_VCTL, tmp); + out_8(pixis_base + PIXIS_VCTL, tmp); } void set_px_go_with_watchdog(void) { u8 tmp; + u8 *pixis_base = (u8 *)PIXIS_BASE; - tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = in_8(pixis_base + PIXIS_VCTL); tmp = tmp & 0x1E; - out8(PIXIS_BASE + PIXIS_VCTL, tmp); + out_8(pixis_base + PIXIS_VCTL, tmp); - tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = in_8(pixis_base + PIXIS_VCTL); tmp = tmp | 0x09; - out8(PIXIS_BASE + PIXIS_VCTL, tmp); + out_8(pixis_base + PIXIS_VCTL, tmp); } @@ -265,15 +275,16 @@ int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { u8 tmp; + u8 *pixis_base = (u8 *)PIXIS_BASE; - tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = in_8(pixis_base + PIXIS_VCTL); tmp = tmp & 0x1E; - out8(PIXIS_BASE + PIXIS_VCTL, tmp); + out_8(pixis_base + PIXIS_VCTL, tmp); /* setting VCTL[WDEN] to 0 to disable watch dog */ - tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp = in_8(pixis_base + PIXIS_VCTL); tmp &= ~0x08; - out8(PIXIS_BASE + PIXIS_VCTL, tmp); + out_8(pixis_base + PIXIS_VCTL, tmp); return 0; } @@ -288,6 +299,7 @@ U_BOOT_CMD( int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int which_tsec = -1; + u8 *pixis_base = (u8 *)PIXIS_BASE; uchar mask; uchar switch_mask; @@ -328,17 +340,15 @@ int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* Toggle whether the switches or FPGA control the settings */ if (!strcmp(argv[argc - 1], "switch")) - clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1, - switch_mask); + clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask); else - setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VCFGEN1, - switch_mask); + setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask); /* If it's not the switches, enable or disable SGMII, as specified */ if (!strcmp(argv[argc - 1], "on")) - clrbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask); + clrbits_8(pixis_base + PIXIS_VSPEED2, mask); else if (!strcmp(argv[argc - 1], "off")) - setbits_8((unsigned char *)PIXIS_BASE + PIXIS_VSPEED2, mask); + setbits_8(pixis_base + PIXIS_VSPEED2, mask); return 0; } diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index f80b0ba..dea4d6f 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -24,6 +24,7 @@ */ #include <common.h> +#include <hwconfig.h> #include <i2c.h> #include <libfdt.h> #include <fdt_support.h> @@ -176,20 +177,15 @@ void pci_init_board(void) #if defined(CONFIG_OF_BOARD_SETUP) void fdt_tsec1_fixup(void *fdt, bd_t *bd) { - char *mpc8315erdb = getenv("mpc8315erdb"); const char disabled[] = "disabled"; const char *path; int ret; - if (!mpc8315erdb) + if (hwconfig_arg_cmp("board_type", "tsec1")) { return; - - if (!strcmp(mpc8315erdb, "tsec1")) { - return; - } else if (strcmp(mpc8315erdb, "ulpi")) { - printf("WARNING: wrong `mpc8315erdb' environment " - "variable specified: `%s'. Should be `ulpi' " - "or `tsec1'.\n", mpc8315erdb); + } else if (!hwconfig_arg_cmp("board_type", "ulpi")) { + printf("NOTICE: No or unknown board_type hwconfig specified.\n" + " Assuming board with TSEC1.\n"); return; } diff --git a/board/freescale/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile index a97116c..c34905c 100644 --- a/board/freescale/mpc832xemds/Makefile +++ b/board/freescale/mpc832xemds/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c index 212fb52..e1dd757 100644 --- a/board/freescale/mpc832xemds/pci.c +++ b/board/freescale/mpc832xemds/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -16,62 +16,78 @@ #include <asm/mmu.h> #include <asm/io.h> #include <common.h> +#include <mpc83xx.h> #include <pci.h> #include <i2c.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif - #include <asm/fsl_i2c.h> +#include "../common/pq-mds-pib.h" DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_PCI) -#define PCI_FUNCTION_CONFIG 0x44 -#define PCI_FUNCTION_CFG_LOCK 0x20 +static struct pci_region pci1_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, +}; -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxemds_config_table[] = { +#ifdef CONFIG_MPC83XX_PCI2 +static struct pci_region pci2_regions[] = { { - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, - {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} + bus_start: CONFIG_SYS_PCI2_MEM_BASE, + phys_start: CONFIG_SYS_PCI2_MEM_PHYS, + size: CONFIG_SYS_PCI2_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, - {} -} -#endif -static struct pci_controller hose[] = { { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxemds_config_table, -#endif + bus_start: CONFIG_SYS_PCI2_IO_BASE, + phys_start: CONFIG_SYS_PCI2_IO_PHYS, + size: CONFIG_SYS_PCI2_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI2_MMIO_BASE, + phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, + size: CONFIG_SYS_PCI2_MMIO_SIZE, + flags: PCI_REGION_MEM }, }; +#endif + +DECLARE_GLOBAL_DATA_PTR; + -/********************************************************************** - * pci_init_board() - *********************************************************************/ void pci_init_board(void) #ifdef CONFIG_PCISLAVE { - u16 reg16; - volatile immap_t *immr; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; + struct pci_region *reg[] = { pci1_regions }; + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; + + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; + + mpc83xx_pci_init(1, reg, 0); - immr = (immap_t *) CONFIG_SYS_IMMR; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; /* * Configure PCI Inbound Translation Windows */ @@ -90,61 +106,24 @@ void pci_init_board(void) pci_ctrl[0].piebar2 = 0x0; pci_ctrl[0].piwar2 &= ~PIWAR_EN; - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - pci_setup_indirect(&hose[0], - (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); - reg16 = 0xff; - - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), - PCI_LATENCY_TIMER, 0x80); - - /* - * Unlock configuration lock in PCI function configuration register. - */ - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, ®16); - reg16 &= ~(PCI_FUNCTION_CFG_LOCK); - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, reg16); - - printf("Enabled PCI 32bit Agent Mode\n"); + /* Unlock the configuration bit */ + mpc83xx_pcislave_unlock(0); + printf("PCI: Agent mode enabled\n"); } #else { - volatile immap_t *immr; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; +#ifndef CONFIG_MPC83XX_PCI2 + struct pci_region *reg[] = { pci1_regions }; +#else + struct pci_region *reg[] = { pci1_regions, pci2_regions }; +#endif - u16 reg16; - u32 val32; - u32 dev; + /* initialize the PCA9555PW IO expander on the PIB board */ + pib_init(); - immr = (immap_t *) CONFIG_SYS_IMMR; - clk = (clk83xx_t *) & immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - val32 = clk->occr; - udelay(2000); #if defined(PCI_66M) clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; printf("PCI clock is 66MHz\n"); @@ -158,129 +137,19 @@ void pci_init_board(void) #endif udelay(2000); - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI mem space - prefetch */ - pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = - POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI mmio - non-prefetch mem space */ - pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI IO space */ - pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; - pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = - PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | - PIWAR_IWS_2G; - - /* - * Release PCI RST Output signal - */ udelay(2000); - pci_ctrl[0].gcr = 1; - udelay(2000); - - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose[0].regions + 0, - CONFIG_SYS_PCI_MEM_BASE, - CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose[0].regions + 1, - CONFIG_SYS_PCI_MMIO_BASE, - CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose[0].regions + 2, - CONFIG_SYS_PCI_IO_BASE, - CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose[0].regions + 3, - CONFIG_SYS_PCI_SLV_MEM_LOCAL, - CONFIG_SYS_PCI_SLV_MEM_BUS, - CONFIG_SYS_PCI_SLV_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - hose[0].region_count = 4; - - pci_setup_indirect(&hose[0], - (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); - - pci_register_hose(hose); - - /* - * Write command register - */ - reg16 = 0xff; - dev = PCI_BDF(0, 0, 0); - pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); +#ifndef CONFIG_MPC83XX_PCI2 + mpc83xx_pci_init(1, reg, 0); +#else + mpc83xx_pci_init(2, reg, 0); +#endif } #endif /* CONFIG_PCISLAVE */ - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci0", NULL); - if (path) { - tmp[0] = cpu_to_be32(hose[0].first_busno); - tmp[1] = cpu_to_be32(hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } - } -} -#endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile index a97116c..c34905c 100644 --- a/board/freescale/mpc8349emds/Makefile +++ b/board/freescale/mpc8349emds/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index af0b1da..9293f70 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -1,4 +1,6 @@ /* + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. + * * See file CREDITS for list of people who contributed to this * project. * @@ -29,8 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_PCI - static struct pci_region pci1_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, @@ -207,5 +207,3 @@ void pci_init_board(void) printf("PCI: Agent mode enabled\n"); } #endif /* CONFIG_PCISLAVE */ - -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile index c81ba66..527420b 100644 --- a/board/freescale/mpc8349itx/Makefile +++ b/board/freescale/mpc8349itx/Makefile @@ -1,5 +1,5 @@ # -# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# Copyright (C) Freescale Semiconductor, Inc. 2006. # # See file CREDITS for list of people who contributed to this # project. @@ -24,8 +24,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8349itx/config.mk b/board/freescale/mpc8349itx/config.mk index 79f1765..61b6a90 100644 --- a/board/freescale/mpc8349itx/config.mk +++ b/board/freescale/mpc8349itx/config.mk @@ -1,5 +1,5 @@ # -# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# Copyright (C) Freescale Semiconductor, Inc. 2006. # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 35285b4..7da39f1 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -1,5 +1,5 @@ /* - * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Copyright (C) Freescale Semiconductor, Inc. 2006. * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c index 8da7117..38baff3 100644 --- a/board/freescale/mpc8349itx/pci.c +++ b/board/freescale/mpc8349itx/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -22,91 +22,70 @@ #include <common.h> -#ifdef CONFIG_PCI - #include <asm/mmu.h> -#include <asm/global_data.h> +#include <asm/io.h> +#include <mpc83xx.h> #include <pci.h> -#include <asm/mpc8349_pci.h> #include <i2c.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif +#include <asm/fsl_i2c.h> DECLARE_GLOBAL_DATA_PTR; -/* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc8349itx_config_table[] = { +static struct pci_region pci1_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + }, { - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - PCI_ANY_ID, - PCI_IDSEL_NUMBER, - PCI_ANY_ID, - pci_cfgfunc_config_device, - { - PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} - }, - {} + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, }; -#endif -static struct pci_controller pci_hose[] = { +#ifdef CONFIG_MPC83XX_PCI2 +static struct pci_region pci2_regions[] = { { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349itx_config_table, -#endif - }, + bus_start: CONFIG_SYS_PCI2_MEM_BASE, + phys_start: CONFIG_SYS_PCI2_MEM_PHYS, + size: CONFIG_SYS_PCI2_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349itx_config_table, -#endif - } + bus_start: CONFIG_SYS_PCI2_IO_BASE, + phys_start: CONFIG_SYS_PCI2_IO_PHYS, + size: CONFIG_SYS_PCI2_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI2_MMIO_BASE, + phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, + size: CONFIG_SYS_PCI2_MMIO_SIZE, + flags: PCI_REGION_MEM + }, }; +#endif -/************************************************************************** - * pci_init_board() - * - * NOTICE: PCI2 is not currently supported - * - */ void pci_init_board(void) { - volatile immap_t *immr; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; +#ifndef CONFIG_MPC83XX_PCI2 + struct pci_region *reg[] = { pci1_regions }; +#else + struct pci_region *reg[] = { pci1_regions, pci2_regions }; +#endif u8 reg8; - u16 reg16; - u32 reg32; - u32 dev; - struct pci_controller *hose; - - immr = (immap_t *) CONFIG_SYS_IMMR; - clk = (clk83xx_t *) & immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - - hose = &pci_hose[0]; - - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - - reg32 = clk->occr; - udelay(2000); #ifdef CONFIG_HARD_I2C i2c_set_bus_num(1); @@ -123,250 +102,20 @@ void pci_init_board(void) #else clk->occr = 0xff000000; /* 66 MHz PCI */ #endif - - udelay(2000); - - /* - * Release PCI RST Output signal - */ - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - -#ifdef CONFIG_MPC83XX_PCI2 - pci_ctrl[1].gcr = 0; udelay(2000); - pci_ctrl[1].gcr = 1; -#endif - - /* We need to wait at least a 1sec based on PCI specs */ - { - int i; - for (i = 0; i < 1000; i++) - udelay(1000); - } - - /* - * Configure PCI Local Access Windows - */ + /* Configure PCI Local Access Windows */ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI1 mem space - prefetch */ - pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M; - - /* PCI1 IO space */ - pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M; - - /* PCI1 mmio - non-prefetch mem space */ - pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M; - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI1_MEM_BASE, - CONFIG_SYS_PCI1_MEM_PHYS, - CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI1_MMIO_BASE, - CONFIG_SYS_PCI1_MMIO_PHYS, CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CONFIG_SYS_PCI1_IO_BASE, - CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); - -#ifdef CONFIG_MPC83XX_PCI2 - hose = &pci_hose[1]; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI2 mem space - prefetch */ - pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M; - - /* PCI2 IO space */ - pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M; - - /* PCI2 mmio - non-prefetch mem space */ - pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M; - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[1].pitar1 = 0x0; - pci_ctrl[1].pibar1 = 0x0; - pci_ctrl[1].piebar1 = 0x0; - pci_ctrl[1].piwar1 = - PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | - (__ilog2(gd->ram_size) - 1); - - hose->first_busno = pci_hose[0].last_busno + 1; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CONFIG_SYS_PCI2_MEM_BASE, - CONFIG_SYS_PCI2_MEM_PHYS, - CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CONFIG_SYS_PCI2_MMIO_BASE, - CONFIG_SYS_PCI2_MMIO_PHYS, CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CONFIG_SYS_PCI2_IO_BASE, - CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CONFIG_SYS_IMMR + 0x8380), (CONFIG_SYS_IMMR + 0x8384)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word(hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); -#endif -} - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci0", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } -#ifdef CONFIG_MPC83XX_PCI2 - path = fdt_getprop(blob, nodeoffset, "pci1", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); + udelay(2000); - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } +#ifndef CONFIG_MPC83XX_PCI2 + mpc83xx_pci_init(1, reg, 0); +#else + mpc83xx_pci_init(2, reg, 0); #endif - } } -#endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8360emds/Makefile b/board/freescale/mpc8360emds/Makefile index a97116c..c34905c 100644 --- a/board/freescale/mpc8360emds/Makefile +++ b/board/freescale/mpc8360emds/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c index 7ac35dc..04a802b 100644 --- a/board/freescale/mpc8360emds/pci.c +++ b/board/freescale/mpc8360emds/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -13,65 +13,79 @@ /* * PCI Configuration space access support for MPC83xx PCI Bridge */ + #include <asm/mmu.h> #include <asm/io.h> #include <common.h> +#include <mpc83xx.h> #include <pci.h> #include <i2c.h> -#if defined(CONFIG_OF_LIBFDT) -#include <libfdt.h> -#include <fdt_support.h> -#endif - #include <asm/fsl_i2c.h> +#include "../common/pq-mds-pib.h" DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_PCI) -#define PCI_FUNCTION_CONFIG 0x44 -#define PCI_FUNCTION_CFG_LOCK 0x20 +static struct pci_region pci1_regions[] = { + { + bus_start: CONFIG_SYS_PCI1_MEM_BASE, + phys_start: CONFIG_SYS_PCI1_MEM_PHYS, + size: CONFIG_SYS_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CONFIG_SYS_PCI1_IO_BASE, + phys_start: CONFIG_SYS_PCI1_IO_PHYS, + size: CONFIG_SYS_PCI1_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI1_MMIO_BASE, + phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, + size: CONFIG_SYS_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, +}; -/* - * Initialize PCI Devices, report devices found - */ -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc83xxemds_config_table[] = { +#ifdef CONFIG_MPC83XX_PCI2 +static struct pci_region pci2_regions[] = { { - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - pci_cfgfunc_config_device, - {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} - }, - {} -} -#endif -static struct pci_controller hose[] = { + bus_start: CONFIG_SYS_PCI2_MEM_BASE, + phys_start: CONFIG_SYS_PCI2_MEM_PHYS, + size: CONFIG_SYS_PCI2_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc83xxemds_config_table, -#endif - }, + bus_start: CONFIG_SYS_PCI2_IO_BASE, + phys_start: CONFIG_SYS_PCI2_IO_PHYS, + size: CONFIG_SYS_PCI2_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CONFIG_SYS_PCI2_MMIO_BASE, + phys_start: CONFIG_SYS_PCI2_MMIO_PHYS, + size: CONFIG_SYS_PCI2_MMIO_SIZE, + flags: PCI_REGION_MEM + }, }; +#endif -/********************************************************************** - * pci_init_board() - *********************************************************************/ void pci_init_board(void) #ifdef CONFIG_PCISLAVE { - u16 reg16; - volatile immap_t *immr; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; + struct pci_region *reg[] = { pci1_regions }; + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; + + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; + + mpc83xx_pci_init(1, reg, 0); - immr = (immap_t *) CONFIG_SYS_IMMR; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; /* * Configure PCI Inbound Translation Windows */ @@ -90,61 +104,24 @@ void pci_init_board(void) pci_ctrl[0].piebar2 = 0x0; pci_ctrl[0].piwar2 &= ~PIWAR_EN; - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - pci_setup_indirect(&hose[0], - (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); - reg16 = 0xff; - - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0), - PCI_LATENCY_TIMER, 0x80); - - /* - * Unlock configuration lock in PCI function configuration register. - */ - pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, ®16); - reg16 &= ~(PCI_FUNCTION_CFG_LOCK); - pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0), - PCI_FUNCTION_CONFIG, reg16); - - printf("Enabled PCI 32bit Agent Mode\n"); + /* Unlock the configuration bit */ + mpc83xx_pcislave_unlock(0); + printf("PCI: Agent mode enabled\n"); } #else { - volatile immap_t *immr; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - volatile pot83xx_t *pci_pot; - volatile pcictrl83xx_t *pci_ctrl; - volatile pciconf83xx_t *pci_conf; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; +#ifndef CONFIG_MPC83XX_PCI2 + struct pci_region *reg[] = { pci1_regions }; +#else + struct pci_region *reg[] = { pci1_regions, pci2_regions }; +#endif - u16 reg16; - u32 val32; - u32 dev; + /* initialize the PCA9555PW IO expander on the PIB board */ + pib_init(); - immr = (immap_t *) CONFIG_SYS_IMMR; - clk = (clk83xx_t *) & immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - val32 = clk->occr; - udelay(2000); #if defined(PCI_66M) clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2; printf("PCI clock is 66MHz\n"); @@ -158,129 +135,19 @@ void pci_init_board(void) #endif udelay(2000); - /* - * Configure PCI Local Access Windows - */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI mem space - prefetch */ - pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = - POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI mmio - non-prefetch mem space */ - pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI IO space */ - pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; - pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = - PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | - PIWAR_IWS_2G; - - /* - * Release PCI RST Output signal - */ - udelay(2000); - pci_ctrl[0].gcr = 1; udelay(2000); - hose[0].first_busno = 0; - hose[0].last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose[0].regions + 0, - CONFIG_SYS_PCI_MEM_BASE, - CONFIG_SYS_PCI_MEM_PHYS, - CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose[0].regions + 1, - CONFIG_SYS_PCI_MMIO_BASE, - CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose[0].regions + 2, - CONFIG_SYS_PCI_IO_BASE, - CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose[0].regions + 3, - CONFIG_SYS_PCI_SLV_MEM_LOCAL, - CONFIG_SYS_PCI_SLV_MEM_BUS, - CONFIG_SYS_PCI_SLV_MEM_SIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose[0].region_count = 4; - - pci_setup_indirect(&hose[0], - (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); - - pci_register_hose(hose); - - /* - * Write command register - */ - reg16 = 0xff; - dev = PCI_BDF(0, 0, 0); - pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08); - - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); +#ifndef CONFIG_MPC83XX_PCI2 + mpc83xx_pci_init(1, reg, 0); +#else + mpc83xx_pci_init(2, reg, 0); +#endif } #endif /* CONFIG_PCISLAVE */ - -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci0", NULL); - if (path) { - tmp[0] = cpu_to_be32(hose[0].first_busno); - tmp[1] = cpu_to_be32(hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } - } -} -#endif /* CONFIG_OF_LIBFDT */ -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc837xemds/Makefile b/board/freescale/mpc837xemds/Makefile index a97116c..c34905c 100644 --- a/board/freescale/mpc837xemds/Makefile +++ b/board/freescale/mpc837xemds/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 8506892..9d8b18d 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -11,6 +11,7 @@ */ #include <common.h> +#include <hwconfig.h> #include <i2c.h> #include <asm/io.h> #include <asm/fsl_serdes.h> @@ -18,12 +19,12 @@ #include <tsec.h> #include <libfdt.h> #include <fdt_support.h> +#include <fsl_esdhc.h> #include "pci.h" #include "../common/pq-mds-pib.h" int board_early_init_f(void) { - struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; /* Enable flash write */ @@ -31,18 +32,6 @@ int board_early_init_f(void) /* Clear all of the interrupt of BCSR */ bcsr[0xe] = 0xff; -#ifdef CONFIG_MMC - /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */ - bcsr[0xc] |= 0x4c; - - /* Set proper bits in SICR to allow SD signals through */ - clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); - - clrsetbits_be32(&im->sysconf.sicrh, (SICRH_GPIO2_E | SICRH_SPI), - (SICRH_GPIO2_E_SD | SICRH_SPI_SD)); - -#endif - #ifdef CONFIG_FSL_SERDES immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; u32 spridr = in_be32(&immr->sysconf.spridr); @@ -72,6 +61,27 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bd) +{ + struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; + + if (!hwconfig("esdhc")) + return 0; + + /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */ + bcsr[0xc] |= 0x4c; + + /* Set proper bits in SICR to allow SD signals through */ + clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); + clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI, + SICRH_GPIO2_E_SD | SICRH_SPI_SD); + + return fsl_esdhc_mmc_init(bd); +} +#endif + #if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) int board_eth_init(bd_t *bd) { @@ -282,10 +292,9 @@ int board_pci_host_broken(void) { struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST; - const char *pci_ea = getenv("pci_external_arbiter"); /* It's always OK in case of external arbiter. */ - if (pci_ea && !strcmp(pci_ea, "yes")) + if (hwconfig_subarg_cmp("pci", "arbiter", "external")) return 0; if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask) @@ -322,6 +331,7 @@ void ft_board_setup(void *blob, bd_t *bd) ft_cpu_setup(blob, bd); ft_tsec_fixup(blob, bd); fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); #ifdef CONFIG_PCI ft_pci_setup(blob, bd); if (board_pci_host_broken()) diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c index 29de2e7..6b7b8b2 100644 --- a/board/freescale/mpc837xemds/pci.c +++ b/board/freescale/mpc837xemds/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -20,7 +20,6 @@ #include <asm/fsl_i2c.h> #include <asm/fsl_serdes.h> -#if defined(CONFIG_PCI) static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI_MEM_BASE, @@ -152,4 +151,3 @@ void ft_pcie_fixup(void *blob, bd_t *bd) do_fixup_by_path(blob, "pci2", "status", status, strlen(status) + 1, 1); } -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile index a97116c..c34905c 100644 --- a/board/freescale/mpc837xerdb/Makefile +++ b/board/freescale/mpc837xerdb/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS := $(BOARD).o pci.o +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_PCI) += pci.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index a4a1927..c5c2e40 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -13,12 +13,14 @@ */ #include <common.h> +#include <hwconfig.h> #include <i2c.h> #include <asm/io.h> #include <asm/fsl_serdes.h> #include <fdt_support.h> #include <spd_sdram.h> #include <vsc7385.h> +#include <fsl_esdhc.h> #if defined(CONFIG_SYS_DRAM_TEST) int @@ -166,6 +168,21 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bd) +{ + struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; + + if (!hwconfig("esdhc")) + return 0; + + clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); + clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD); + + return fsl_esdhc_mmc_init(bd); +} +#endif + /* * Miscellaneous late-boot configurations * @@ -195,5 +212,6 @@ void ft_board_setup(void *blob, bd_t *bd) #endif ft_cpu_setup(blob, bd); fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); } #endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c index 83e89cf..97ad227 100644 --- a/board/freescale/mpc837xerdb/pci.c +++ b/board/freescale/mpc837xerdb/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -15,7 +15,6 @@ #include <pci.h> #include <asm/io.h> -#if defined(CONFIG_PCI) static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI_MEM_BASE, @@ -113,4 +112,3 @@ void pci_init_board(void) mpc83xx_pcie_init(2, pcie_reg, 0); } -#endif /* CONFIG_PCI */ diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 28b27ee..8c5984b 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -60,10 +60,41 @@ int board_early_init_f (void) int checkboard (void) { - printf ("Board: MPC8536DS, System ID: 0x%02x, " - "System Version: 0x%02x, FPGA Version: 0x%02x\n", - in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), - in8(PIXIS_BASE + PIXIS_PVER)); + u8 vboot; + u8 *pixis_base = (u8 *)PIXIS_BASE; + + puts("Board: MPC8536DS "); +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap) "); +#endif + + printf ("Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), + in_8(pixis_base + PIXIS_PVER)); + + vboot = in_8(pixis_base + PIXIS_VBOOT); + switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { + case PIXIS_VBOOT_LBMAP_NOR0: + puts ("vBank: 0\n"); + break; + case PIXIS_VBOOT_LBMAP_NOR1: + puts ("vBank: 1\n"); + break; + case PIXIS_VBOOT_LBMAP_NOR2: + puts ("vBank: 2\n"); + break; + case PIXIS_VBOOT_LBMAP_NOR3: + puts ("vBank: 3\n"); + break; + case PIXIS_VBOOT_LBMAP_PJET: + puts ("Promjet\n"); + break; + case PIXIS_VBOOT_LBMAP_NAND: + puts ("NAND\n"); + break; + } + return 0; } @@ -498,20 +529,24 @@ ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) unsigned long get_board_sys_clk(ulong dummy) { + u8 *pixis_base = (u8 *)PIXIS_BASE; + return ics307_clk_freq ( - in8(PIXIS_BASE + PIXIS_VSYSCLK0), - in8(PIXIS_BASE + PIXIS_VSYSCLK1), - in8(PIXIS_BASE + PIXIS_VSYSCLK2) + in_8(pixis_base + PIXIS_VSYSCLK0), + in_8(pixis_base + PIXIS_VSYSCLK1), + in_8(pixis_base + PIXIS_VSYSCLK2) ); } unsigned long get_board_ddr_clk(ulong dummy) { + u8 *pixis_base = (u8 *)PIXIS_BASE; + return ics307_clk_freq ( - in8(PIXIS_BASE + PIXIS_VDDRCLK0), - in8(PIXIS_BASE + PIXIS_VDDRCLK1), - in8(PIXIS_BASE + PIXIS_VDDRCLK2) + in_8(pixis_base + PIXIS_VDDRCLK0), + in_8(pixis_base + PIXIS_VDDRCLK1), + in_8(pixis_base + PIXIS_VDDRCLK2) ); } #else @@ -520,8 +555,9 @@ get_board_sys_clk(ulong dummy) { u8 i; ulong val = 0; + u8 *pixis_base = (u8 *)PIXIS_BASE; - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); i &= 0x07; switch (i) { @@ -559,8 +595,9 @@ get_board_ddr_clk(ulong dummy) { u8 i; ulong val = 0; + u8 *pixis_base = (u8 *)PIXIS_BASE; - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); i &= 0x38; i >>= 3; diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 34bdbad..fd59839 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -43,14 +43,22 @@ int checkboard (void) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + u8 vboot; + u8 *pixis_base = (u8 *)PIXIS_BASE; if ((uint)&gur->porpllsr != 0xe00e0000) { printf("immap size error %lx\n",(ulong)&gur->porpllsr); } - printf ("Board: MPC8544DS, System ID: 0x%02x, " - "System Version: 0x%02x, FPGA Version: 0x%02x\n", - in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), - in8(PIXIS_BASE + PIXIS_PVER)); + printf ("Board: MPC8544DS, Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), + in_8(pixis_base + PIXIS_PVER)); + + vboot = in_8(pixis_base + PIXIS_VBOOT); + if (vboot & PIXIS_VBOOT_FMAP) + printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); + else + puts ("Promjet\n"); lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ @@ -383,11 +391,12 @@ get_board_sys_clk(ulong dummy) { u8 i, go_bit, rd_clks; ulong val = 0; + u8 *pixis_base = (u8 *)PIXIS_BASE; - go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit = in_8(pixis_base + PIXIS_VCTL); go_bit &= 0x01; - rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); rd_clks &= 0x1C; /* @@ -398,11 +407,11 @@ get_board_sys_clk(ulong dummy) if (go_bit) { if (rd_clks == 0x1c) - i = in8(PIXIS_BASE + PIXIS_AUX); + i = in_8(pixis_base + PIXIS_AUX); else - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); } else { - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); } i &= 0x07; diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c index a936edb..b688e5c 100644 --- a/board/freescale/mpc8569mds/bcsr.c +++ b/board/freescale/mpc8569mds/bcsr.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. + * Copyright (C) 2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h index e5d63c7..c4738d7 100644 --- a/board/freescale/mpc8569mds/bcsr.h +++ b/board/freescale/mpc8569mds/bcsr.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. + * Copyright (C) 2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/freescale/mpc8569mds/config.mk b/board/freescale/mpc8569mds/config.mk index 36b344e..8895cda 100644 --- a/board/freescale/mpc8569mds/config.mk +++ b/board/freescale/mpc8569mds/config.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. +# Copyright (C) 2009 Freescale Semiconductor, Inc. # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 4b95617..7c86134 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -42,14 +42,34 @@ long int fixed_sdram(void); int checkboard (void) { + u8 vboot; + u8 *pixis_base = (u8 *)PIXIS_BASE; + puts ("Board: MPC8572DS "); #ifdef CONFIG_PHYS_64BIT puts ("(36-bit addrmap) "); #endif printf ("Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n", - in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), - in8(PIXIS_BASE + PIXIS_PVER)); + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), + in_8(pixis_base + PIXIS_PVER)); + + vboot = in_8(pixis_base + PIXIS_VBOOT); + switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) { + case PIXIS_VBOOT_LBMAP_NOR0: + puts ("vBank: 0\n"); + break; + case PIXIS_VBOOT_LBMAP_PJET: + puts ("Promjet\n"); + break; + case PIXIS_VBOOT_LBMAP_NAND: + puts ("NAND\n"); + break; + case PIXIS_VBOOT_LBMAP_NOR1: + puts ("vBank: 1\n"); + break; + } + return 0; } @@ -412,19 +432,23 @@ ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2) unsigned long get_board_sys_clk(ulong dummy) { + u8 *pixis_base = (u8 *)PIXIS_BASE; + return ics307_clk_freq ( - in8(PIXIS_BASE + PIXIS_VSYSCLK0), - in8(PIXIS_BASE + PIXIS_VSYSCLK1), - in8(PIXIS_BASE + PIXIS_VSYSCLK2) + in_8(pixis_base + PIXIS_VSYSCLK0), + in_8(pixis_base + PIXIS_VSYSCLK1), + in_8(pixis_base + PIXIS_VSYSCLK2) ); } unsigned long get_board_ddr_clk(ulong dummy) { + u8 *pixis_base = (u8 *)PIXIS_BASE; + return ics307_clk_freq ( - in8(PIXIS_BASE + PIXIS_VDDRCLK0), - in8(PIXIS_BASE + PIXIS_VDDRCLK1), - in8(PIXIS_BASE + PIXIS_VDDRCLK2) + in_8(pixis_base + PIXIS_VDDRCLK0), + in_8(pixis_base + PIXIS_VDDRCLK1), + in_8(pixis_base + PIXIS_VDDRCLK2) ); } #else @@ -432,8 +456,9 @@ unsigned long get_board_sys_clk(ulong dummy) { u8 i; ulong val = 0; + u8 *pixis_base = (u8 *)PIXIS_BASE; - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); i &= 0x07; switch (i) { @@ -470,8 +495,9 @@ unsigned long get_board_ddr_clk(ulong dummy) { u8 i; ulong val = 0; + u8 *pixis_base = (u8 *)PIXIS_BASE; - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); i &= 0x38; i >>= 3; diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index a85ebea..2ac169b 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -55,16 +55,17 @@ int board_early_init_f(void) int misc_init_r(void) { u8 tmp_val, version; + u8 *pixis_base = (u8 *)PIXIS_BASE; /*Do not use 8259PIC*/ - tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); - out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80); + tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); + out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ - version = in8(PIXIS_BASE + PIXIS_PVER); + version = in_8(pixis_base + PIXIS_PVER); if(version >= 0x07) { - tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); - out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf); + tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); + out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); } /* Using this for DIU init before the driver in linux takes over @@ -96,11 +97,12 @@ int checkboard(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; + u8 *pixis_base = (u8 *)PIXIS_BASE; printf ("Board: MPC8610HPCD, System ID: 0x%02x, " "System Version: 0x%02x, FPGA Version: 0x%02x\n", - in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), - in8(PIXIS_BASE + PIXIS_PVER)); + in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), + in_8(pixis_base + PIXIS_PVER)); mcm->abcr |= 0x00010000; /* 0 */ mcm->hpmr3 = 0x80000008; /* 4c */ @@ -154,7 +156,7 @@ phys_size_t fixed_sdram(void) ddr->timing_cfg_0 = 0x00260802; ddr->timing_cfg_1 = 0x3935d322; ddr->timing_cfg_2 = 0x14904cc8; - ddr->sdram_mode_1 = 0x00480432; + ddr->sdram_mode = 0x00480432; ddr->sdram_mode_2 = 0x00000000; ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ ddr->sdram_data_init = 0xDEADBEEF; @@ -170,7 +172,7 @@ phys_size_t fixed_sdram(void) udelay(500); - ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/ + ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) @@ -438,10 +440,9 @@ get_board_sys_clk(ulong dummy) { u8 i; ulong val = 0; - ulong a; + u8 *pixis_base = (u8 *)PIXIS_BASE; - a = PIXIS_BASE + PIXIS_SPD; - i = in8(a); + i = in_8(pixis_base + PIXIS_SPD); i &= 0x07; switch (i) { @@ -481,7 +482,9 @@ int board_eth_init(bd_t *bis) void board_reset(void) { - out8(PIXIS_BASE + PIXIS_RST, 0); + u8 *pixis_base = (u8 *)PIXIS_BASE; + + out_8(pixis_base + PIXIS_RST, 0); while (1) ; diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index 0ad878c..4186a2e 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -33,7 +33,7 @@ #include "../common/fsl_diu_fb.h" #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) -#include <devices.h> +#include <stdio_dev.h> #include <video_fb.h> #endif @@ -69,9 +69,10 @@ void mpc8610hpcd_diu_init(void) unsigned int pixel_format; unsigned char tmp_val; unsigned char pixis_arch; + u8 *pixis_base = (u8 *)PIXIS_BASE; - tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0); - pixis_arch = in8(PIXIS_BASE + PIXIS_VER); + tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); + pixis_arch = in_8(pixis_base + PIXIS_VER); monitor_port = getenv("monitor"); if (!strncmp(monitor_port, "0", 1)) { /* 0 - DVI */ @@ -82,28 +83,28 @@ void mpc8610hpcd_diu_init(void) else pixel_format = 0x88883316; gamma_fix = 0; - out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08); + out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08); } else if (!strncmp(monitor_port, "1", 1)) { /* 1 - Single link LVDS */ xres = 1024; yres = 768; pixel_format = 0x88883316; gamma_fix = 0; - out8(PIXIS_BASE + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10); + out_8(pixis_base + PIXIS_BRDCFG0, (tmp_val & 0xf7) | 0x10); } else if (!strncmp(monitor_port, "2", 1)) { /* 2 - Double link LVDS */ xres = 1280; yres = 1024; pixel_format = 0x88883316; gamma_fix = 1; - out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xe7); + out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xe7); } else { /* DVI */ xres = 1280; yres = 1024; pixel_format = 0x88882317; gamma_fix = 0; - out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x08); + out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08); } fsl_diu_init(xres, pixel_format, gamma_fix, diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 7422e6b..a8b2112 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -42,10 +42,20 @@ int board_early_init_f(void) int checkboard(void) { - printf ("Board: MPC8641HPCN, System ID: 0x%02x, " - "System Version: 0x%02x, FPGA Version: 0x%02x\n", - in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), - in8(PIXIS_BASE + PIXIS_PVER)); + u8 vboot; + u8 *pixis_base = (u8 *)PIXIS_BASE; + + printf ("Board: MPC8641HPCN, Sys ID: 0x%02x, " + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), + in_8(pixis_base + PIXIS_PVER)); + + vboot = in_8(pixis_base + PIXIS_VBOOT); + if (vboot & PIXIS_VBOOT_FMAP) + printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6)); + else + puts ("Promjet\n"); + #ifdef CONFIG_PHYS_64BIT printf (" 36-bit physical address map\n"); #endif @@ -91,7 +101,7 @@ fixed_sdram(void) ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; - ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1; + ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; @@ -109,9 +119,9 @@ fixed_sdram(void) #if defined (CONFIG_DDR_ECC) /* Enable ECC checking */ - ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000); + ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000); #else - ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL; + ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL; ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2; #endif asm("sync; isync"); @@ -300,11 +310,12 @@ get_board_sys_clk(ulong dummy) { u8 i, go_bit, rd_clks; ulong val = 0; + u8 *pixis_base = (u8 *)PIXIS_BASE; - go_bit = in8(PIXIS_BASE + PIXIS_VCTL); + go_bit = in_8(pixis_base + PIXIS_VCTL); go_bit &= 0x01; - rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0); + rd_clks = in_8(pixis_base + PIXIS_VCFGEN0); rd_clks &= 0x1C; /* @@ -315,11 +326,11 @@ get_board_sys_clk(ulong dummy) if (go_bit) { if (rd_clks == 0x1c) - i = in8(PIXIS_BASE + PIXIS_AUX); + i = in_8(pixis_base + PIXIS_AUX); else - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); } else { - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); } i &= 0x07; @@ -363,7 +374,9 @@ int board_eth_init(bd_t *bis) void board_reset(void) { - out8(PIXIS_BASE + PIXIS_RST, 0); + u8 *pixis_base = (u8 *)PIXIS_BASE; + + out_8(pixis_base + PIXIS_RST, 0); while (1) ; diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 6b60c17..9f47169 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -25,6 +25,7 @@ #include <common.h> +#include <netdev.h> #include <asm/arch/mx31.h> #include <asm/arch/mx31-regs.h> @@ -61,3 +62,12 @@ int checkboard(void) printf("Board: i.MX31 MAX PDK (3DS)\n"); return 0; } + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 293e5a4..14de7e7 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -47,14 +47,31 @@ phys_size_t fixed_sdram(void); int checkboard(void) { + u8 sw7; + u8 *pixis_base = (u8 *)PIXIS_BASE; + puts("Board: P2020DS "); #ifdef CONFIG_PHYS_64BIT puts("(36-bit addrmap) "); #endif + printf("Sys ID: 0x%02x, " - "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n", - in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), - in8(PIXIS_BASE + PIXIS_PVER)); + "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", + in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), + in_8(pixis_base + PIXIS_PVER)); + + sw7 = in_8(pixis_base + PIXIS_SW(7)); + switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) { + case 0: + case 1: + printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4)); + break; + case 2: + case 3: + puts ("Promjet\n"); + break; + } + return 0; } @@ -462,10 +479,12 @@ unsigned long calculate_board_sys_clk(ulong dummy) { ulong val; + u8 *pixis_base = (u8 *)PIXIS_BASE; + val = ics307_clk_freq( - in8(PIXIS_BASE + PIXIS_VSYSCLK0), - in8(PIXIS_BASE + PIXIS_VSYSCLK1), - in8(PIXIS_BASE + PIXIS_VSYSCLK2)); + in_8(pixis_base + PIXIS_VSYSCLK0), + in_8(pixis_base + PIXIS_VSYSCLK1), + in_8(pixis_base + PIXIS_VSYSCLK2)); debug("sysclk val = %lu\n", val); return val; } @@ -474,10 +493,12 @@ unsigned long calculate_board_ddr_clk(ulong dummy) { ulong val; + u8 *pixis_base = (u8 *)PIXIS_BASE; + val = ics307_clk_freq( - in8(PIXIS_BASE + PIXIS_VDDRCLK0), - in8(PIXIS_BASE + PIXIS_VDDRCLK1), - in8(PIXIS_BASE + PIXIS_VDDRCLK2)); + in_8(pixis_base + PIXIS_VDDRCLK0), + in_8(pixis_base + PIXIS_VDDRCLK1), + in_8(pixis_base + PIXIS_VDDRCLK2)); debug("ddrclk val = %lu\n", val); return val; } @@ -486,8 +507,9 @@ unsigned long get_board_sys_clk(ulong dummy) { u8 i; ulong val = 0; + u8 *pixis_base = (u8 *)PIXIS_BASE; - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); i &= 0x07; switch (i) { @@ -524,8 +546,9 @@ unsigned long get_board_ddr_clk(ulong dummy) { u8 i; ulong val = 0; + u8 *pixis_base = (u8 *)PIXIS_BASE; - i = in8(PIXIS_BASE + PIXIS_SPD); + i = in_8(pixis_base + PIXIS_SPD); i &= 0x38; i >>= 3; |