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-rw-r--r--board/freescale/mpc8536ds/mpc8536ds.c16
-rw-r--r--board/freescale/mpc8540ads/mpc8540ads.c2
-rw-r--r--board/freescale/mpc8541cds/mpc8541cds.c2
-rw-r--r--board/freescale/mpc8544ds/mpc8544ds.c16
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c27
-rw-r--r--board/freescale/mpc8555cds/mpc8555cds.c2
-rw-r--r--board/freescale/mpc8560ads/mpc8560ads.c2
-rw-r--r--board/freescale/mpc8568mds/mpc8568mds.c14
-rw-r--r--board/freescale/mpc8572ds/mpc8572ds.c28
-rw-r--r--board/freescale/mpc8572ds/tlb.c7
-rw-r--r--board/freescale/mpc8610hpcd/law.c4
-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd.c12
12 files changed, 32 insertions, 100 deletions
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 6fed4ea..2b17612 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -41,10 +41,6 @@
#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
phys_size_t fixed_sdram(void);
int checkboard (void)
@@ -65,20 +61,12 @@ initdram(int board_type)
#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
- dram_size *= 0x100000;
#else
dram_size = fixed_sdram();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
puts(" DDR: ");
return dram_size;
}
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index a0b6fbd..9e3f677 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -133,7 +133,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 7e40c5c..e6025c8 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -308,7 +308,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 545d869..9777312 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -38,10 +38,6 @@
#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -77,12 +73,6 @@ initdram(int board_type)
dram_size *= 0x100000;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
puts(" DDR: ");
return dram_size;
}
@@ -131,7 +121,7 @@ pci_init_board(void)
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 1);
- int pcie_configured = io_sel >= 1;
+ int pcie_configured = io_sel >= 6;
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -198,7 +188,7 @@ pci_init_board(void)
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent == 5);
- int pcie_configured = io_sel & 6;
+ int pcie_configured = io_sel >= 2;
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -261,7 +251,7 @@ pci_init_board(void)
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 3);
- int pcie_configured = io_sel & 4;
+ int pcie_configured = io_sel >= 4;
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index af5ff42..90e89bc 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -38,10 +38,6 @@
#include "../common/eeprom.h"
#include "../common/via.h"
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void);
@@ -56,7 +52,6 @@ int checkboard (void)
uint pci_slot = get_pci_slot ();
uint cpu_board_rev = get_cpu_board_revision ();
- uint svr;
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot);
@@ -69,17 +64,6 @@ int checkboard (void)
*/
local_bus_init ();
- svr = get_svr();
-
- /*
- * Fix CPU2 errata: A core hang possible while executing a
- * msync instruction and a snoopable transaction from an I/O
- * master tagged to make quick forward progress is present.
- * Fixed in Silicon Rev.2.1
- */
- if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
- ecm->eebpcr |= (1 << 16);
-
/*
* Hack TSEC 3 and 4 IO voltages.
*/
@@ -118,13 +102,6 @@ initdram(int board_type)
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
/*
* SDRAM Initialization
*/
@@ -148,7 +125,7 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & 0x0f) * 2;
+ clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
@@ -355,7 +332,7 @@ pci_init_board(void)
first_free_busno=hose->last_busno+1;
printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
#ifdef CONFIG_PCIX_CHECK
- if (!(gur->pordevsr & PORDEVSR_PCI)) {
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
/* PCI-X init */
if (CONFIG_SYS_CLK_FREQ < 66000000)
printf("PCI-X will only work at 66 MHz\n");
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index 33685c1..53d5a93 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -308,7 +308,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 3730818..ac7778e 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -337,7 +337,7 @@ local_bus_init(void)
*/
get_sys_info(&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
if (lbc_hz < 66) {
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 688d8c3..7a23b33 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -99,11 +99,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
void local_bus_init(void);
void sdram_init(void);
@@ -170,13 +165,6 @@ initdram(int board_type)
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
/*
* SDRAM Initialization
*/
@@ -200,7 +188,7 @@ local_bus_init(void)
sys_info_t sysinfo;
get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & 0x0f) * 2;
+ clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 3a78c98..c2487e5 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -38,10 +38,6 @@
#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
long int fixed_sdram(void);
int checkboard (void)
@@ -61,20 +57,12 @@ phys_size_t initdram(int board_type)
#ifdef CONFIG_SPD_EEPROM
dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
- dram_size *= 0x100000;
#else
dram_size = fixed_sdram();
#endif
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
puts(" DDR: ");
return dram_size;
}
@@ -178,11 +166,11 @@ void pci_init_board(void)
struct pci_controller *hose = &pcie3_hose;
int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
(host_agent == 5) || (host_agent == 6);
- int pcie_configured = io_sel >= 1;
+ int pcie_configured = (io_sel == 0x7);
struct pci_region *r = hose->regions;
u32 temp32;
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
printf ("\n PCIE3 connected to ULI as %s (base address %x)",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
@@ -246,10 +234,10 @@ void pci_init_board(void)
struct pci_controller *hose = &pcie2_hose;
int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
(host_agent == 6) || (host_agent == 0);
- int pcie_configured = io_sel & 4;
+ int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7);
struct pci_region *r = hose->regions;
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
pcie_ep ? "End Point" : "Root Complex",
(uint)pci);
@@ -299,7 +287,9 @@ void pci_init_board(void)
struct pci_controller *hose = &pcie1_hose;
int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
(host_agent == 5);
- int pcie_configured = io_sel & 6;
+ int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) ||
+ (io_sel == 0x7) || (io_sel == 0xb) ||
+ (io_sel == 0xc) || (io_sel == 0xf);
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
index 8d1f646..829896a 100644
--- a/board/freescale/mpc8572ds/tlb.c
+++ b/board/freescale/mpc8572ds/tlb.c
@@ -41,10 +41,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_4K, 0),
-
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
@@ -86,6 +82,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
+ SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_4K, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c
index 2aad28a..0fc8384 100644
--- a/board/freescale/mpc8610hpcd/law.c
+++ b/board/freescale/mpc8610hpcd/law.c
@@ -31,8 +31,8 @@ struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
#endif
- SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CONFIG_SYS_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 2792778..a2097a5 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -266,14 +266,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
@@ -321,14 +321,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BASE,
+ CONFIG_SYS_PCIE2_MEM_BUS,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BASE,
+ CONFIG_SYS_PCIE2_IO_BUS,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
@@ -370,14 +370,14 @@ void pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
generated by cgit v1.1 at 2024-12-29 16:41:26 +0000