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-rw-r--r--board/freescale/common/pixis.c472
-rw-r--r--board/freescale/common/pixis.h31
-rw-r--r--board/freescale/mpc8544ds/Makefile58
-rw-r--r--board/freescale/mpc8544ds/config.mk32
-rw-r--r--board/freescale/mpc8544ds/init.S243
-rw-r--r--board/freescale/mpc8544ds/mpc8544ds.c201
-rw-r--r--board/freescale/mpc8544ds/u-boot.lds148
7 files changed, 1185 insertions, 0 deletions
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
new file mode 100644
index 0000000..af98157
--- /dev/null
+++ b/board/freescale/common/pixis.c
@@ -0,0 +1,472 @@
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include "pixis.h"
+
+
+static ulong strfractoint(uchar *strptr);
+
+
+/*
+ * Simple board reset.
+ */
+void pixis_reset(void)
+{
+ out8(PIXIS_BASE + PIXIS_RST, 0);
+}
+
+
+/*
+ * Per table 27, page 58 of MPC8641HPCN spec.
+ */
+int set_px_sysclk(ulong sysclk)
+{
+ u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
+
+ switch (sysclk) {
+ case 33:
+ sysclk_s = 0x04;
+ sysclk_r = 0x04;
+ sysclk_v = 0x07;
+ sysclk_aux = 0x00;
+ break;
+ case 40:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x20;
+ sysclk_aux = 0x01;
+ break;
+ case 50:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x2A;
+ sysclk_aux = 0x02;
+ break;
+ case 66:
+ sysclk_s = 0x01;
+ sysclk_r = 0x04;
+ sysclk_v = 0x04;
+ sysclk_aux = 0x03;
+ break;
+ case 83:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x4B;
+ sysclk_aux = 0x04;
+ break;
+ case 100:
+ sysclk_s = 0x01;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x5C;
+ sysclk_aux = 0x05;
+ break;
+ case 134:
+ sysclk_s = 0x06;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x3B;
+ sysclk_aux = 0x06;
+ break;
+ case 166:
+ sysclk_s = 0x06;
+ sysclk_r = 0x1F;
+ sysclk_v = 0x4B;
+ sysclk_aux = 0x07;
+ break;
+ default:
+ printf("Unsupported SYSCLK frequency.\n");
+ return 0;
+ }
+
+ vclkh = (sysclk_s << 5) | sysclk_r;
+ vclkl = sysclk_v;
+
+ out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
+ out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
+
+ out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
+
+ return 1;
+}
+
+
+int set_px_mpxpll(ulong mpxpll)
+{
+ u8 tmp;
+ u8 val;
+
+ switch (mpxpll) {
+ case 2:
+ case 4:
+ case 6:
+ case 8:
+ case 10:
+ case 12:
+ case 14:
+ case 16:
+ val = (u8) mpxpll;
+ break;
+ default:
+ printf("Unsupported MPXPLL ratio.\n");
+ return 0;
+ }
+
+ tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
+ tmp = (tmp & 0xF0) | (val & 0x0F);
+ out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
+
+ return 1;
+}
+
+
+int set_px_corepll(ulong corepll)
+{
+ u8 tmp;
+ u8 val;
+
+ switch ((int)corepll) {
+ case 20:
+ val = 0x08;
+ break;
+ case 25:
+ val = 0x0C;
+ break;
+ case 30:
+ val = 0x10;
+ break;
+ case 35:
+ val = 0x1C;
+ break;
+ case 40:
+ val = 0x14;
+ break;
+ case 45:
+ val = 0x0E;
+ break;
+ default:
+ printf("Unsupported COREPLL ratio.\n");
+ return 0;
+ }
+
+ tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
+ tmp = (tmp & 0xE0) | (val & 0x1F);
+ out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
+
+ return 1;
+}
+
+
+void read_from_px_regs(int set)
+{
+ u8 mask = 0x1C;
+ u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+
+ if (set)
+ tmp = tmp | mask;
+ else
+ tmp = tmp & ~mask;
+ out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
+}
+
+
+void read_from_px_regs_altbank(int set)
+{
+ u8 mask = 0x04;
+ u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
+
+ if (set)
+ tmp = tmp | mask;
+ else
+ tmp = tmp & ~mask;
+ out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
+}
+
+
+void set_altbank(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
+ tmp ^= 0x40;
+
+ out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
+}
+
+
+void set_px_go(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp | 0x01;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+void set_px_go_with_watchdog(void)
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp | 0x09;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
+ int flag, int argc, char *argv[])
+{
+ u8 tmp;
+
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp = tmp & 0x1E;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ /* setting VCTL[WDEN] to 0 to disable watch dog */
+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+ tmp &= ~0x08;
+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ diswd, 1, 0, pixis_disable_watchdog_cmd,
+ "diswd - Disable watchdog timer \n",
+ NULL);
+
+/*
+ * This function takes the non-integral cpu:mpx pll ratio
+ * and converts it to an integer that can be used to assign
+ * FPGA register values.
+ * input: strptr i.e. argv[2]
+ */
+
+static ulong strfractoint(uchar *strptr)
+{
+ int i, j, retval;
+ int mulconst;
+ int intarr_len = 0, decarr_len = 0, no_dec = 0;
+ ulong intval = 0, decval = 0;
+ uchar intarr[3], decarr[3];
+
+ /* Assign the integer part to intarr[]
+ * If there is no decimal point i.e.
+ * if the ratio is an integral value
+ * simply create the intarr.
+ */
+ i = 0;
+ while (strptr[i] != 46) {
+ if (strptr[i] == 0) {
+ no_dec = 1;
+ break;
+ }
+ intarr[i] = strptr[i];
+ i++;
+ }
+
+ /* Assign length of integer part to intarr_len. */
+ intarr_len = i;
+ intarr[i] = '\0';
+
+ if (no_dec) {
+ /* Currently needed only for single digit corepll ratios */
+ mulconst = 10;
+ decval = 0;
+ } else {
+ j = 0;
+ i++; /* Skipping the decimal point */
+ while ((strptr[i] > 47) && (strptr[i] < 58)) {
+ decarr[j] = strptr[i];
+ i++;
+ j++;
+ }
+
+ decarr_len = j;
+ decarr[j] = '\0';
+
+ mulconst = 1;
+ for (i = 0; i < decarr_len; i++)
+ mulconst *= 10;
+ decval = simple_strtoul(decarr, NULL, 10);
+ }
+
+ intval = simple_strtoul(intarr, NULL, 10);
+ intval = intval * mulconst;
+
+ retval = intval + decval;
+
+ return retval;
+}
+
+
+int
+pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ ulong val;
+ ulong corepll;
+
+ /*
+ * No args is a simple reset request.
+ */
+ if (argc <= 1) {
+ pixis_reset();
+ /* not reached */
+ }
+
+ if (strcmp(argv[1], "cf") == 0) {
+
+ /*
+ * Reset with frequency changed:
+ * cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ */
+ if (argc < 5) {
+ puts(cmdtp->usage);
+ return 1;
+ }
+
+ read_from_px_regs(0);
+
+ val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
+
+ corepll = strfractoint(argv[3]);
+ val = val + set_px_corepll(corepll);
+ val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
+ if (val == 3) {
+ puts("Setting registers VCFGEN0 and VCTL\n");
+ read_from_px_regs(1);
+ puts("Resetting board with values from ");
+ puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
+ set_px_go();
+ } else {
+ puts(cmdtp->usage);
+ return 1;
+ }
+
+ while (1) ; /* Not reached */
+
+ } else if (strcmp(argv[1], "altbank") == 0) {
+
+ /*
+ * Reset using alternate flash bank:
+ */
+ if (argv[2] == 0) {
+ /*
+ * Reset from alternate bank without changing
+ * frequency and without watchdog timer enabled.
+ * altbank
+ */
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ if (argc > 2) {
+ puts(cmdtp->usage);
+ return 1;
+ }
+ puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs_altbank(1);
+ puts("Resetting board to boot from the other bank.\n");
+ set_px_go();
+
+ } else if (strcmp(argv[2], "cf") == 0) {
+ /*
+ * Reset with frequency changed
+ * altbank cf <SYSCLK freq> <COREPLL ratio>
+ * <MPXPLL ratio>
+ */
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
+ corepll = strfractoint(argv[4]);
+ val = val + set_px_corepll(corepll);
+ val = val + set_px_mpxpll(simple_strtoul(argv[5],
+ NULL, 10));
+ if (val == 3) {
+ puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs(1);
+ read_from_px_regs_altbank(1);
+ puts("Enabling watchdog timer on the FPGA\n");
+ puts("Resetting board with values from ");
+ puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
+ puts("to boot from the other bank.\n");
+ set_px_go_with_watchdog();
+ } else {
+ puts(cmdtp->usage);
+ return 1;
+ }
+
+ while (1) ; /* Not reached */
+
+ } else if (strcmp(argv[2], "wd") == 0) {
+ /*
+ * Reset from alternate bank without changing
+ * frequencies but with watchdog timer enabled:
+ * altbank wd
+ */
+ read_from_px_regs(0);
+ read_from_px_regs_altbank(0);
+ puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
+ set_altbank();
+ read_from_px_regs_altbank(1);
+ puts("Enabling watchdog timer on the FPGA\n");
+ puts("Resetting board to boot from the other bank.\n");
+ set_px_go_with_watchdog();
+ while (1) ; /* Not reached */
+
+ } else {
+ puts(cmdtp->usage);
+ return 1;
+ }
+
+ } else {
+ puts(cmdtp->usage);
+ return 1;
+ }
+
+ return 0;
+}
+
+
+U_BOOT_CMD(
+ pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
+ "pixis_reset - Reset the board using the FPGA sequencer\n",
+ " pixis_reset\n"
+ " pixis_reset [altbank]\n"
+ " pixis_reset altbank wd\n"
+ " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
+ " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
+ );
diff --git a/board/freescale/common/pixis.h b/board/freescale/common/pixis.h
new file mode 100644
index 0000000..ff62a62
--- /dev/null
+++ b/board/freescale/common/pixis.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2006 Freescale Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+extern void pixis_reset(void);
+extern int set_px_sysclk(ulong sysclk);
+extern int set_px_mpxpll(ulong mpxpll);
+extern int set_px_corepll(ulong corepll);
+extern void read_from_px_regs(int set);
+extern void read_from_px_regs_altbank(int set);
+extern void set_altbank(void);
+extern void set_px_go(void);
+extern void set_px_go_with_watchdog(void);
diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile
new file mode 100644
index 0000000..bec2168
--- /dev/null
+++ b/board/freescale/mpc8544ds/Makefile
@@ -0,0 +1,58 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# ifneq ($(OBJTREE),$(SRCTREE))
+# $(shell mkdir -p $(obj)./common)
+# endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o \
+ ../common/pixis.o
+
+SOBJS := init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8544ds/config.mk b/board/freescale/mpc8544ds/config.mk
new file mode 100644
index 0000000..85663ef
--- /dev/null
+++ b/board/freescale/mpc8544ds/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8544ds board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xfff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8544=1
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
new file mode 100644
index 0000000..296fee5
--- /dev/null
+++ b/board/freescale/mpc8544ds/init.S
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define LAWAR_TRGT_PCI1 0x00000000
+#define LAWAR_TRGT_PCIE1 0x00200000
+#define LAWAR_TRGT_PCIE2 0x00100000
+#define LAWAR_TRGT_PCIE3 0x00300000
+#define LAWAR_TRGT_LBC 0x00400000
+#define LAWAR_TRGT_DDR 0x00f00000
+
+/*
+ * TLB0 and TLB1 Entries
+ *
+ * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
+ * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
+ * these TLB entries are established.
+ *
+ * The TLB entries for DDR are dynamically setup in spd_sdram()
+ * and use TLB1 Entries 8 through 15 as needed according to the
+ * size of DDR memory.
+ *
+ * MAS0: tlbsel, esel, nv
+ * MAS1: valid, iprot, tid, ts, tsize
+ * MAS2: epn, sharen, x0, x1, w, i, m, g, e
+ * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
+ */
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ /*
+ * Number of TLB0 and TLB1 entries in the following table
+ */
+ .long (2f-1f)/16
+1:
+ /*
+ * TLB0 4K Non-cacheable, guarded
+ * 0xff700000 4K Initial CCSRBAR mapping
+ *
+ * This ends up at a TLB0 Index==0 entry, and must not collide
+ * with other TLB0 Entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB0 16K Cacheable, guarded
+ * Temporary Global data for initialization
+ *
+ * Use four 4K TLB0 entries. These entries must be cacheable
+ * as they provide the bootstrap memory before the memory
+ * controler and real memory have been configured.
+ *
+ * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
+ * and must not collide with other TLB0 entries.
+ */
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(0, 0, 0)
+ .long TLB1_MAS1(1, 0, 0, 0, 0)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
+ 0,0,0,0,0,1,0,1,0,1)
+
+
+ /*
+ * TLB 0: 64M Non-cacheable, guarded
+ * 0xfc000000 64M Covers FLASH at 0xFE800000 and 0xFF800000
+ * Out of reset this entry is only 4K.
+ */
+ .long TLB1_MAS0(1, 0, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 1: 1G Non-cacheable, guarded
+ * 0x80000000 1G PCIE 8,9,a,b
+ */
+ .long TLB1_MAS0(1, 1, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCIE_PHYS),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCIE_PHYS),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 2: 256M Non-cacheable, guarded
+ */
+ .long TLB1_MAS0(1, 2, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 3: 256M Non-cacheable, guarded
+ */
+ .long TLB1_MAS0(1, 3, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+
+ /*
+ * TLB 4: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe100_0000 255M PCI IO range
+ */
+ .long TLB1_MAS0(1, 4, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
+
+#ifdef CFG_LBC_CACHE_BASE
+ /*
+ * TLB 5: 64M Cacheable, non-guarded
+ */
+ .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+#endif
+ /*
+ * TLB 6: 64M Non-cacheable, guarded
+ * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
+ */
+ .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+2:
+ entry_end
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *
+ * Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+
+ .long (4f-3f)/8
+3:
+ .long 0
+ .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+
+ .long (CFG_PCI1_MEM_BASE>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+
+ .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+
+ .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
+
+ /* To keep to 10 LAWs, PCIE1_IO_PHYS must use top of mem region */
+
+ .long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+
+ .long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+
+ .long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_256M)
+
+ .long (CFG_PCIE3_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_16M)
+4:
+ entry_end
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
new file mode 100644
index 0000000..4ff1da9
--- /dev/null
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+#include <miiphy.h>
+
+#include "../common/pixis.h"
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+ return 0;
+}
+
+int checkboard (void)
+{
+ volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+
+ if ((uint)&gur->porpllsr != 0xe00e0000) {
+ printf("immap size error %x\n",&gur->porpllsr);
+ }
+ printf ("Board: MPC8544DS\n");
+
+ return 0;
+}
+
+long int
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+ dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ /*
+ * Initialize and enable DDR ECC.
+ */
+ ddr_enable_ecc(dram_size);
+#endif
+ puts(" DDR: ");
+ return dram_size;
+}
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("Testing DRAM from 0x%08x to 0x%08x\n",
+ CFG_MEMTEST_START,
+ CFG_MEMTEST_END);
+
+ printf("DRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("DRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("DRAM test passed.\n");
+ return 0;
+}
+#endif
+
+int last_stage_init(void)
+{
+ return 0;
+}
+
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+ u8 i, go_bit, rd_clks;
+ ulong val = 0;
+
+ go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+ go_bit &= 0x01;
+
+ rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+ rd_clks &= 0x1C;
+
+ /*
+ * Only if both go bit and the SCLK bit in VCFGEN0 are set
+ * should we be using the AUX register. Remember, we also set the
+ * GO bit to boot from the alternate bank on the on-board flash
+ */
+
+ if (go_bit) {
+ if (rd_clks == 0x1c)
+ i = in8(PIXIS_BASE + PIXIS_AUX);
+ else
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ } else {
+ i = in8(PIXIS_BASE + PIXIS_SPD);
+ }
+
+ i &= 0x07;
+
+ switch (i) {
+ case 0:
+ val = 33333333;
+ break;
+ case 1:
+ val = 40000000;
+ break;
+ case 2:
+ val = 50000000;
+ break;
+ case 3:
+ val = 66666666;
+ break;
+ case 4:
+ val = 83000000;
+ break;
+ case 5:
+ val = 100000000;
+ break;
+ case 6:
+ val = 133333333;
+ break;
+ case 7:
+ val = 166666666;
+ break;
+ }
+
+ return val;
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
+}
+#endif
diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds
new file mode 100644
index 0000000..1a8aaa9
--- /dev/null
+++ b/board/freescale/mpc8544ds/u-boot.lds
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/freescale/mpc8544ds/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/freescale/mpc8544ds/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
generated by cgit v1.1 at 2024-11-25 10:44:17 +0000