summaryrefslogtreecommitdiff
path: root/board/freescale
diff options
context:
space:
mode:
Diffstat (limited to 'board/freescale')
-rw-r--r--board/freescale/mpc8572ds/mpc8572ds.c6
-rw-r--r--board/freescale/p1_p2_rdb/pci.c4
-rw-r--r--board/freescale/p2020ds/p2020ds.c6
3 files changed, 8 insertions, 8 deletions
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 933dd12..2b32234 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -199,7 +199,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno);
+ &pcie3_hose, first_free_busno, pcie_ep);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
@@ -231,7 +231,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
+ &pcie2_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE2: disabled\n");
}
@@ -251,7 +251,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
+ &pcie1_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE1: disabled\n");
}
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
index 4c08f9e..7736596 100644
--- a/board/freescale/p1_p2_rdb/pci.c
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -71,7 +71,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
+ &pcie2_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE2: disabled\n");
}
@@ -90,7 +90,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
+ &pcie1_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE1: disabled\n");
}
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index e38c014..9878fba 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -227,7 +227,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
+ &pcie2_hose, first_free_busno, pcie_ep);
/*
* The workaround doesn't work on p2020 because the location
@@ -267,7 +267,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno);
+ &pcie3_hose, first_free_busno, pcie_ep);
} else {
printf(" PCIE3: disabled\n");
}
@@ -286,7 +286,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
+ &pcie1_hose, first_free_busno, pcie_ep);
} else {
printf(" PCIE1: disabled\n");
}