diff options
Diffstat (limited to 'board/freescale')
-rw-r--r-- | board/freescale/ls1021aqds/ls1021aqds.c | 68 | ||||
-rw-r--r-- | board/freescale/ls1021atwr/ls1021atwr.c | 27 |
2 files changed, 69 insertions, 26 deletions
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 722b88f..69a5671 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -138,6 +138,17 @@ unsigned long get_board_ddr_clk(void) return 66666666; } +unsigned int get_soc_major_rev(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr, major; + + svr = in_be32(&gur->svr); + major = SVR_MAJ(svr); + + return major; +} + int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -181,6 +192,7 @@ int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; #ifdef CONFIG_TSEC_ENET out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); @@ -205,19 +217,22 @@ int board_early_init_f(void) out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override Register - * All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - - /* Workaround for the issue that DDR could not respond to - * barrier transaction which is generated by executing DSB/ISB - * instruction. Set CCI-400 control override register to - * terminate the barrier transaction. After DDR is initialized, - * allow barrier transaction to DDR again */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) { + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override + * Register All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + + /* Workaround for the issue that DDR could not respond to + * barrier transaction which is generated by executing DSB/ISB + * instruction. Set CCI-400 control override register to + * terminate the barrier transaction. After DDR is initialized, + * allow barrier transaction to DDR again */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + } #if defined(CONFIG_DEEP_SLEEP) if (is_warm_boot()) @@ -231,6 +246,7 @@ int board_early_init_f(void) void board_init_f(ulong dummy) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; #ifdef CONFIG_NAND_BOOT struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; @@ -267,7 +283,10 @@ void board_init_f(ulong dummy) #ifdef CONFIG_SPL_I2C_SUPPORT i2c_init_all(); #endif - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); dram_init(); @@ -548,10 +567,14 @@ struct smmu_stream_id dev_stream_id[] = { int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; - /* Set CCI-400 control override register to - * enable barrier transaction */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) { + /* Set CCI-400 control override register to + * enable barrier transaction */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + } select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); @@ -580,10 +603,15 @@ int board_init(void) void board_sleep_prepare(void) { struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; + + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) { + /* Set CCI-400 control override register to + * enable barrier transaction */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + } - /* Set CCI-400 control override register to - * enable barrier transaction */ - out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); #ifdef CONFIG_LS102XA_NS_ACCESS enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index fb8525f..a9c87f2 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -122,6 +122,17 @@ int checkboard(void) return 0; } +unsigned int get_soc_major_rev(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr, major; + + svr = in_be32(&gur->svr); + major = SVR_MAJ(svr); + + return major; +} + void ddrmc_init(void) { struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; @@ -264,6 +275,7 @@ int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + unsigned int major; #ifdef CONFIG_TSEC_ENET out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); @@ -289,12 +301,15 @@ int board_early_init_f(void) out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); - /* - * Set CCI-400 Slave interface S1, S2 Shareable Override Register - * All transactions are treated as non-shareable - */ - out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); - out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + major = get_soc_major_rev(); + if (major == SOC_MAJOR_VER_1_0) { + /* + * Set CCI-400 Slave interface S1, S2 Shareable Override + * Register All transactions are treated as non-shareable + */ + out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE); + } return 0; } |