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-rw-r--r--board/freescale/m5208evbe/m5208evbe.c28
-rw-r--r--board/freescale/m52277evb/m52277evb.c30
-rw-r--r--board/freescale/m5235evb/m5235evb.c43
-rw-r--r--board/freescale/m5253demo/m5253demo.c29
-rw-r--r--board/freescale/m5253evbe/m5253evbe.c30
-rw-r--r--board/freescale/m5272c3/m5272c3.c9
-rw-r--r--board/freescale/m5275evb/m5275evb.c50
-rw-r--r--board/freescale/m53017evb/m53017evb.c28
-rw-r--r--board/freescale/m5329evb/m5329evb.c28
-rw-r--r--board/freescale/m5329evb/nand.c14
-rw-r--r--board/freescale/m5373evb/m5373evb.c28
-rw-r--r--board/freescale/m5373evb/nand.c18
-rw-r--r--board/freescale/m54451evb/m54451evb.c32
-rw-r--r--board/freescale/m54455evb/m54455evb.c90
-rw-r--r--board/freescale/m547xevb/m547xevb.c34
-rw-r--r--board/freescale/m548xevb/m548xevb.c34
-rw-r--r--board/freescale/mpc8308rdb/mpc8308rdb.c58
17 files changed, 342 insertions, 241 deletions
diff --git a/board/freescale/m5208evbe/m5208evbe.c b/board/freescale/m5208evbe/m5208evbe.c
index 5f99e2f..355cfed 100644
--- a/board/freescale/m5208evbe/m5208evbe.c
+++ b/board/freescale/m5208evbe/m5208evbe.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,34 +51,35 @@ phys_size_t initdram(int board_type)
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
- sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
asm("nop");
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
asm("nop");
udelay(100);
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
index 9109edb..a9bec58 100644
--- a/board/freescale/m52277evb/m52277evb.c
+++ b/board/freescale/m52277evb/m52277evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -47,8 +48,8 @@ phys_size_t initdram(int board_type)
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -59,36 +60,37 @@ phys_size_t initdram(int board_type)
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
__asm__("nop");
udelay(1000);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
#endif
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index b9e6126..e9a568e 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,8 +40,8 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 dramsize, i, dramclk;
/*
@@ -48,14 +49,15 @@ phys_size_t initdram(int board_type)
* the port-size of SDRAM. In this case it is necessary to enable
* Data[15:0] on Port Address/Data.
*/
- gpio->par_ad =
- GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
- GPIO_PAR_AD_DATAL;
+ out_8(&gpio->par_ad,
+ GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
+ GPIO_PAR_AD_DATAL);
/* Initialize PAR to enable SDRAM signals */
- gpio->par_sdram =
- GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
- GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
+ out_8(&gpio->par_sdram,
+ GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
+ GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
+ GPIO_PAR_SDRAM_SDCS(3));
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
@@ -64,25 +66,28 @@ phys_size_t initdram(int board_type)
}
i--;
- if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
+ if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
/* Initialize DRAM Control Register: DCR */
- sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
- SDRAMC_DCR_RTIM_6CLKS | SDRAMC_DCR_RC((15 * dramclk) >> 4);
+ out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
+ SDRAMC_DCR_RTIM_6CLKS |
+ SDRAMC_DCR_RC((15 * dramclk) >> 4));
/* Initialize DACR0 */
- sdram->dacr0 =
- SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
- SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
+ out_be32(&sdram->dacr0,
+ SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
+ SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
+ SDRAMC_DARCn_PS_32);
asm("nop");
/* Initialize DMR0 */
- sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
+ out_be32(&sdram->dmr0,
+ ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
asm("nop");
/* Set IP (bit 3) in DACR */
- sdram->dacr0 |= SDRAMC_DARCn_IP;
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
/* Wait 30ns to allow banks to precharge */
for (i = 0; i < 5; i++) {
@@ -93,7 +98,7 @@ phys_size_t initdram(int board_type)
*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
/* Set RE (bit 15) in DACR */
- sdram->dacr0 |= SDRAMC_DARCn_RE;
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
/* Wait for at least 8 auto refresh cycles to occur */
for (i = 0; i < 0x2000; i++) {
@@ -101,7 +106,7 @@ phys_size_t initdram(int board_type)
}
/* Finish the configuration by issuing the MRS. */
- sdram->dacr0 |= SDRAMC_DARCn_IMRS;
+ setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
asm("nop");
/* Write to the SDRAM Mode Register */
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 8ffb2cc..052993d 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -109,7 +109,7 @@ int ide_preinit(void)
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+ atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
@@ -120,7 +120,8 @@ void ide_set_reset(int idereset)
};
if (idereset) {
- ata->cr = 0; /* control reset */
+ /* control reset */
+ out_8(&ata->cr, 0);
udelay(100);
} else {
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
@@ -129,17 +130,19 @@ void ide_set_reset(int idereset)
period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
- ata->t1 = CALC_TIMING(piotms[2][0]);
- ata->t2w = CALC_TIMING(piotms[2][1]);
- ata->t2r = CALC_TIMING(piotms[2][1]);
- ata->ta = CALC_TIMING(piotms[2][8]);
- ata->trd = CALC_TIMING(piotms[2][7]);
- ata->t4 = CALC_TIMING(piotms[2][3]);
- ata->t9 = CALC_TIMING(piotms[2][6]);
-
- ata->cr = 0x40; /* IORDY enable */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
udelay(2000);
- ata->cr |= 0x01; /* IORDY enable */
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
}
}
#endif /* CONFIG_CMD_IDE */
diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c
index ae69f67..658748b 100644
--- a/board/freescale/m5253evbe/m5253evbe.c
+++ b/board/freescale/m5253evbe/m5253evbe.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int checkboard(void)
{
@@ -101,7 +102,7 @@ int ide_preinit(void)
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
+ atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
@@ -112,7 +113,8 @@ void ide_set_reset(int idereset)
};
if (idereset) {
- ata->cr = 0; /* control reset */
+ /* control reset */
+ out_8(&ata->cr, 0);
udelay(100);
} else {
mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
@@ -121,17 +123,19 @@ void ide_set_reset(int idereset)
period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
/*ata->ton = CALC_TIMING (180); */
- ata->t1 = CALC_TIMING(piotms[2][0]);
- ata->t2w = CALC_TIMING(piotms[2][1]);
- ata->t2r = CALC_TIMING(piotms[2][1]);
- ata->ta = CALC_TIMING(piotms[2][8]);
- ata->trd = CALC_TIMING(piotms[2][7]);
- ata->t4 = CALC_TIMING(piotms[2][3]);
- ata->t9 = CALC_TIMING(piotms[2][6]);
-
- ata->cr = 0x40; /* IORDY enable */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
udelay(2000);
- ata->cr |= 0x01; /* IORDY enable */
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
}
}
#endif /* CONFIG_CMD_IDE */
diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c
index 902ca3a..c3160ce 100644
--- a/board/freescale/m5272c3/m5272c3.c
+++ b/board/freescale/m5272c3/m5272c3.c
@@ -2,6 +2,8 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -23,6 +25,7 @@
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int checkboard (void) {
@@ -32,10 +35,10 @@ int checkboard (void) {
};
phys_size_t initdram (int board_type) {
- volatile sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
+ sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
- sdp->sdram_sdtr = 0xf539;
- sdp->sdram_sdcr = 0x4211;
+ out_be16(&sdp->sdram_sdtr, 0xf539);
+ out_be16(&sdp->sdram_sdcr, 0x4211);
/* Dummy write to start SDRAM */
*((volatile unsigned long *)0) = 0;
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
index 35c9b20..1bbe5a3 100644
--- a/board/freescale/m5275evb/m5275evb.c
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -4,6 +4,8 @@
*
* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -25,6 +27,7 @@
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
#define PERIOD 13 /* system bus period in ns */
#define SDRAM_TREFI 7800 /* in ns */
@@ -38,67 +41,68 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+ sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
+ gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
- gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
+ /* Enable SDRAM */
+ out_be16(&gpio_reg->par_sdram, 0x3FF);
/* Set up chip select */
- sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE;
- sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
+ out_be32(&sdp->sdbar0, CONFIG_SYS_SDRAM_BASE);
+ out_be32(&sdp->sdbmr0, MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V);
/* Set up timing */
- sdp->sdcfg1 = 0x83711630;
- sdp->sdcfg2 = 0x46770000;
+ out_be32(&sdp->sdcfg1, 0x83711630);
+ out_be32(&sdp->sdcfg2, 0x46770000);
/* Enable clock */
- sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE;
+ out_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE);
/* Set precharge */
- sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
/* Dummy write to start SDRAM */
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */
- sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
- | MCF_SDRAMC_SDMR_AD(0x0)
- | MCF_SDRAMC_SDMR_CMD;
+ setbits_be32(&sdp->sdmr,
+ MCF_SDRAMC_SDMR_BNKAD_LEMR | MCF_SDRAMC_SDMR_AD(0x0) |
+ MCF_SDRAMC_SDMR_CMD);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */
- sdp->sdmr = 0x058d0000;
+ out_be32(&sdp->sdmr, 0x058d0000);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
- sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
/* Set precharge */
- sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */
- sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
- sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IPALL);
+ setbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_IREF);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
- /* Write mode register, clear reset DLL */
- sdp->sdmr = 0x018d0000;
+
+ out_be32(&sdp->sdmr, 0x018d0000);
*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
- sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
- sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
+ clrbits_be32(&sdp->sdmr, MCF_SDRAMC_SDMR_CMD);
+ clrbits_be32(&sdp->sdcr, MCF_SDRAMC_SDCR_MODE_EN);
/* Turn on auto refresh, lock SDMR */
- sdp->sdcr =
+ out_be32(&sdp->sdcr,
MCF_SDRAMC_SDCR_CKE
| MCF_SDRAMC_SDCR_REF
| MCF_SDRAMC_SDCR_MUX(1)
/* 1 added to round up */
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
- | MCF_SDRAMC_SDCR_DQS_OE(0x3);
+ | MCF_SDRAMC_SDCR_DQS_OE(0x3));
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
diff --git a/board/freescale/m53017evb/m53017evb.c b/board/freescale/m53017evb/m53017evb.c
index f331786..142485f 100644
--- a/board/freescale/m53017evb/m53017evb.c
+++ b/board/freescale/m53017evb/m53017evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,34 +51,35 @@ phys_size_t initdram(int board_type)
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_SDRAM_BASE1
- sdram->cs1 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cs1, CONFIG_SYS_SDRAM_BASE | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
asm("nop");
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
asm("nop");
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
asm("nop");
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
asm("nop");
udelay(100);
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
index b4df22f..1c14b83 100644
--- a/board/freescale/m5329evb/m5329evb.c
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,29 +51,30 @@ phys_size_t initdram(int board_type)
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 16025f9..c70c98c 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -67,18 +67,18 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
int board_nand_init(struct nand_chip *nand)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
- gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
- gpio->pddr_timer |= 0x08;
- gpio->ppd_timer |= 0x08;
- gpio->pclrr_timer = 0;
- gpio->podr_timer = 0;
+ clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+ setbits_8(&gpio->pddr_timer, 0x08);
+ setbits_8(&gpio->ppd_timer, 0x08);
+ out_8(&gpio->pclrr_timer, 0);
+ out_8(&gpio->podr_timer, 0);
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index 376de4b..8eb3512 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <config.h>
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -39,7 +40,7 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
@@ -50,29 +51,30 @@ phys_size_t initdram(int board_type)
}
i--;
- sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index df8c03b..ed79e39 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -68,21 +68,21 @@ static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
int board_nand_init(struct nand_chip *nand)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- fbcs->csmr2 &= ~FBCS_CSMR_WP;
+ clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
/*
* set up pin configuration - enabled 2nd output buffer's signals
* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
* to use nCE signal
*/
- gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
- gpio->pddr_timer |= 0x08;
- gpio->ppd_timer |= 0x08;
- gpio->pclrr_timer = 0;
- gpio->podr_timer = 0;
+ clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
+ setbits_8(&gpio->pddr_timer, 0x08);
+ setbits_8(&gpio->ppd_timer, 0x08);
+ out_8(&gpio->pclrr_timer, 0);
+ out_8(&gpio->podr_timer, 0);
nand->chip_delay = 60;
nand->ecc.mode = NAND_ECC_SOFT;
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
index 088c8c4..32a9374 100644
--- a/board/freescale/m54451evb/m54451evb.c
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <common.h>
#include <spi.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -51,14 +52,14 @@ phys_size_t initdram(int board_type)
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
- if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
- (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
+ if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
+ (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
return dramsize;
for (i = 0x13; i < 0x20; i++) {
@@ -67,32 +68,33 @@ phys_size_t initdram(int board_type)
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
udelay(200);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
__asm__("nop");
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
__asm__("nop");
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
__asm__("nop");
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
udelay(100);
#endif
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
index 2a84514..0ca268e 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -47,8 +48,8 @@ phys_size_t initdram(int board_type)
*/
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
#else
- volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
- volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
u32 i;
dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
@@ -59,33 +60,34 @@ phys_size_t initdram(int board_type)
}
i--;
- gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+ out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
- sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
- sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i);
+ out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
- sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408;
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
udelay(500);
/* Issue PALL */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200;
+ out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
- sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+ out_be32(&sdram->sdcr,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
udelay(100);
#endif
@@ -105,26 +107,29 @@ int testdram(void)
int ide_preinit(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
- gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
- gpio->par_feci2c |=
- (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
- GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
- gpio->par_ata |=
- (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
- GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
- | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
- GPIO_PAR_ATA_IORDY_IORDY);
- gpio->par_pci |=
- (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ u32 tmp;
+
+ tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
+ setbits_8(&gpio->par_fec, tmp);
+ tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
+ (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
+ setbits_be16(&gpio->par_feci2c, tmp);
+
+ setbits_be16(&gpio->par_ata,
+ GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
+ GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
+ GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
+ GPIO_PAR_ATA_IORDY_IORDY);
+ setbits_be16(&gpio->par_pci,
+ GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
return (0);
}
void ide_set_reset(int idereset)
{
- volatile atac_t *ata = (atac_t *) MMAP_ATA;
+ atac_t *ata = (atac_t *) MMAP_ATA;
long period;
/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
int piotms[5][9] = {
@@ -136,24 +141,27 @@ void ide_set_reset(int idereset)
}; /* PIO 4 */
if (idereset) {
- ata->cr = 0; /* control reset */
+ /* control reset */
+ out_8(&ata->cr, 0);
udelay(10000);
} else {
#define CALC_TIMING(t) (t + period - 1) / period
period = 1000000000 / gd->bus_clk; /* period in ns */
/*ata->ton = CALC_TIMING (180); */
- ata->t1 = CALC_TIMING(piotms[2][0]);
- ata->t2w = CALC_TIMING(piotms[2][1]);
- ata->t2r = CALC_TIMING(piotms[2][1]);
- ata->ta = CALC_TIMING(piotms[2][8]);
- ata->trd = CALC_TIMING(piotms[2][7]);
- ata->t4 = CALC_TIMING(piotms[2][3]);
- ata->t9 = CALC_TIMING(piotms[2][6]);
-
- ata->cr = 0x40; /* IORDY enable */
+ out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
+ out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
+ out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
+ out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
+ out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
+ out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
+
+ /* IORDY enable */
+ out_8(&ata->cr, 0x40);
udelay(200000);
- ata->cr |= 0x01; /* IORDY enable */
+ /* IORDY enable */
+ setbits_8(&ata->cr, 0x01);
}
}
#endif
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
index 9f1ec38..fd9bddd 100644
--- a/board/freescale/m547xevb/m547xevb.c
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,14 +41,14 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile siu_t *siu = (siu_t *) (MMAP_SIU);
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ siu_t *siu = (siu_t *) (MMAP_SIU);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
#ifdef CONFIG_SYS_DRAMSZ1
u32 temp;
#endif
- siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
+ out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
for (i = 0x13; i < 0x20; i++) {
@@ -55,7 +56,7 @@ phys_size_t initdram(int board_type)
break;
}
i--;
- siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_DRAMSZ1
temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
@@ -65,31 +66,32 @@ phys_size_t initdram(int board_type)
}
i--;
dramsize += temp;
- siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
+ out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
udelay(100);
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c
index fbc0888..fb216d8 100644
--- a/board/freescale/m548xevb/m548xevb.c
+++ b/board/freescale/m548xevb/m548xevb.c
@@ -2,7 +2,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
#include <common.h>
#include <pci.h>
#include <asm/immap.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,14 +41,14 @@ int checkboard(void)
phys_size_t initdram(int board_type)
{
- volatile siu_t *siu = (siu_t *) (MMAP_SIU);
- volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
+ siu_t *siu = (siu_t *) (MMAP_SIU);
+ sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
u32 dramsize, i;
#ifdef CONFIG_SYS_DRAMSZ1
u32 temp;
#endif
- siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
+ out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
for (i = 0x13; i < 0x20; i++) {
@@ -55,7 +56,7 @@ phys_size_t initdram(int board_type)
break;
}
i--;
- siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
+ out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_DRAMSZ1
temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
@@ -65,31 +66,32 @@ phys_size_t initdram(int board_type)
}
i--;
dramsize += temp;
- siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
+ out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
#endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
- sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
+ out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
+ out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */
- sdram->mode = CONFIG_SYS_SDRAM_EMOD;
- sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
- sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
+ out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE;
+ out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+ out_be32(&sdram->ctrl,
+ (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
udelay(100);
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
index 5c54357..7e3fa1a 100644
--- a/board/freescale/mpc8308rdb/mpc8308rdb.c
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -24,18 +24,56 @@
#include <common.h>
#include <hwconfig.h>
#include <i2c.h>
+#include <spi.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <pci.h>
#include <mpc83xx.h>
#include <vsc7385.h>
#include <netdev.h>
+#include <fsl_esdhc.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * The following are used to control the SPI chip selects for the SPI command.
+ */
+#ifdef CONFIG_MPC8XXX_SPI
+
+#define SPI_CS_MASK 0x00400000
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /* active low */
+ clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+
+ /* inactive high */
+ setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+}
+#endif /* CONFIG_MPC8XXX_SPI */
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
static u8 read_board_info(void)
{
u8 val8;
@@ -109,6 +147,25 @@ void pci_init_board(void)
*/
int misc_init_r(void)
{
+#ifdef CONFIG_MPC8XXX_SPI
+ immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ sysconf83xx_t *sysconf = &immr->sysconf;
+
+ /*
+ * Set proper bits in SICRH to allow SPI on header J8
+ *
+ * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
+ * switch. The pinmux configuration does not have a fine enough
+ * granularity to support both simultaneously.
+ */
+ clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
+ puts("WARNING: SPI enabled, TSEC2 support is broken\n");
+
+ /* Set header J8 SPI chip select output, disabled */
+ setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
+ setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
+#endif
+
#ifdef CONFIG_VSC7385_IMAGE
if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
CONFIG_VSC7385_IMAGE_SIZE)) {
@@ -124,6 +181,7 @@ void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
}
#endif
generated by cgit v1.1 at 2024-08-26 10:38:42 +0000