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-rw-r--r--board/freescale/mx51_bbg/lowlevel_init.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/mx51_bbg/lowlevel_init.S b/board/freescale/mx51_bbg/lowlevel_init.S
index 8b9d338..f7f780a 100644
--- a/board/freescale/mx51_bbg/lowlevel_init.S
+++ b/board/freescale/mx51_bbg/lowlevel_init.S
@@ -242,10 +242,10 @@
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
- /* Use default for UART clock */
- ldr r1, =0xA6A2A020
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+ ldr r1, =0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
- ldr r1, =0x00C30318
+ ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
/* make sure divider effective */