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-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd.c6
-rw-r--r--board/freescale/mpc8641hpcn/config.mk2
-rw-r--r--board/freescale/mpc8641hpcn/law.c35
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c66
4 files changed, 61 insertions, 48 deletions
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 159e7d1..2792778 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -37,7 +37,7 @@
#include "../common/pixis.h"
void sdram_init(void);
-long int fixed_sdram(void);
+phys_size_t fixed_sdram(void);
void mpc8610hpcd_diu_init(void);
@@ -117,7 +117,7 @@ int checkboard(void)
phys_size_t
initdram(int board_type)
{
- long dram_size = 0;
+ phys_size_t dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();
@@ -140,7 +140,7 @@ initdram(int board_type)
* Fixed sdram init -- doesn't use serial presence detect.
*/
-long int fixed_sdram(void)
+phys_size_t fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
diff --git a/board/freescale/mpc8641hpcn/config.mk b/board/freescale/mpc8641hpcn/config.mk
index f778dcb..487a766 100644
--- a/board/freescale/mpc8641hpcn/config.mk
+++ b/board/freescale/mpc8641hpcn/config.mk
@@ -25,7 +25,7 @@
# default CCSRBAR is at 0xff700000
# assume U-Boot is less than 0.5MB
#
-TEXT_BASE = 0xfff00000
+TEXT_BASE = 0xeff00000
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 8e13728..bd357b8 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -31,17 +31,21 @@
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
+ * if PCI (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
- * 0xf800_0000 0xf80f_ffff CCSRBAR 1M
- * 0xf810_0000 0xf81f_ffff PIXIS 1M
- * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
+ * else if RIO (prepend 0xc_0000_0000 if CONFIG_PHYS_64BIT)
+ * 0x8000_0000 0x9fff_ffff RapidIO 512M
+ * endif
+ * (prepend 0xf_0000_0000 if CONFIG_PHYS_64BIT)
+ * 0xffc0_0000 0xffc0_ffff PCI1 IO 64K
+ * 0xffc1_0000 0xffc1_ffff PCI2 IO 64K
+ * 0xffe0_0000 0xffef_ffff CCSRBAR 1M
+ * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K
+ * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M
*
* Notes:
- * CCSRBAR don't need a configured Local Access Window.
+ * CCSRBAR doesn't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
@@ -49,13 +53,16 @@ struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
#endif
- SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
- SET_LAW((CONFIG_SYS_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
+#ifdef CONFIG_PCI
+ SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1),
+ SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2),
+#elif defined(CONFIG_RIO)
+ SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif
+ SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index cccb63e..b83ed6c 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -33,7 +33,7 @@
#include "../common/pixis.h"
-long int fixed_sdram(void);
+phys_size_t fixed_sdram(void);
int board_early_init_f(void)
{
@@ -53,7 +53,7 @@ int checkboard(void)
phys_size_t
initdram(int board_type)
{
- long dram_size = 0;
+ phys_size_t dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
dram_size = fsl_ddr_sdram();
@@ -75,7 +75,7 @@ initdram(int board_type)
/*
* Fixed sdram init -- doesn't use serial presence detect.
*/
-long int
+phys_size_t
fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
@@ -121,27 +121,7 @@ fixed_sdram(void)
#if defined(CONFIG_PCI)
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_fsl86xxads_config_table[] = {
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_IDSEL_NUMBER, PCI_ANY_ID,
- pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
- {}
-};
-#endif
-
-
-static struct pci_controller pci1_hose = {
-#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc86xxcts_config_table
-#endif
-};
+static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI */
#ifdef CONFIG_PCI2
@@ -155,17 +135,16 @@ extern void fsl_pci_init(struct pci_controller *hose);
void pci_init_board(void)
{
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
- >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
-
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = &pci1_hose;
struct pci_region *r = hose->regions;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
+ >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
@@ -275,6 +254,10 @@ extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
void
ft_board_setup(void *blob, bd_t *bd)
{
+ int off;
+ u64 *tmp;
+ u32 *addrcells;
+
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI1
@@ -283,6 +266,29 @@ ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_PCI2
ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
+
+ /*
+ * Warn if it looks like the device tree doesn't match u-boot.
+ * This is just an estimation, based on the location of CCSR,
+ * which is defined by the "reg" property in the soc node.
+ */
+ off = fdt_path_offset(blob, "/soc8641");
+ addrcells = (u32 *)fdt_getprop(blob, 0, "#address-cells", NULL);
+ tmp = (u64 *)fdt_getprop(blob, off, "reg", NULL);
+
+ if (tmp) {
+ u64 addr;
+ if (addrcells && (*addrcells == 1))
+ addr = *(u32 *)tmp;
+ else
+ addr = *tmp;
+
+ if (addr != CONFIG_SYS_CCSRBAR_PHYS)
+ printf("WARNING: The CCSRBAR address in your .dts "
+ "does not match the address of the CCSR "
+ "in u-boot. This means your .dts might "
+ "be old.\n");
+ }
}
#endif
generated by cgit v1.1 at 2024-12-01 19:15:34 +0000