diff options
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/b4860qds/Makefile | 54 | ||||
| -rw-r--r-- | board/freescale/b4860qds/b4860qds.c | 458 | ||||
| -rw-r--r-- | board/freescale/b4860qds/b4860qds.h | 26 | ||||
| -rw-r--r-- | board/freescale/b4860qds/b4860qds_crossbar_con.h | 67 | ||||
| -rw-r--r-- | board/freescale/b4860qds/b4860qds_qixis.h | 37 | ||||
| -rw-r--r-- | board/freescale/b4860qds/ddr.c | 190 | ||||
| -rw-r--r-- | board/freescale/b4860qds/eth_b4860qds.c | 338 | ||||
| -rw-r--r-- | board/freescale/b4860qds/law.c | 44 | ||||
| -rw-r--r-- | board/freescale/b4860qds/pci.c | 39 | ||||
| -rw-r--r-- | board/freescale/b4860qds/tlb.c | 127 |
10 files changed, 1380 insertions, 0 deletions
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile new file mode 100644 index 0000000..06018f4 --- /dev/null +++ b/board/freescale/b4860qds/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-$(CONFIG_B4860QDS)+= eth_b4860qds.o +COBJS-$(CONFIG_PCI) += pci.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c new file mode 100644 index 0000000..88bdc1f --- /dev/null +++ b/board/freescale/b4860qds/b4860qds.c @@ -0,0 +1,458 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <i2c.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> +#include <fm_eth.h> + +#include "../common/qixis.h" +#include "../common/vsc3316_3308.h" +#include "b4860qds.h" +#include "b4860qds_qixis.h" +#include "b4860qds_crossbar_con.h" + +#define CLK_MUX_SEL_MASK 0x4 +#define ETH_PHY_CLK_OUT 0x4 + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + char buf[64]; + u8 sw; + struct cpu_type *cpu = gd->cpu; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; + static const char *const freq[] = {"100", "125", "156.25", "161.13", + "122.88", "122.88", "122.88"}; + int clock; + + printf("Board: %sQDS, ", cpu->name); + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", + QIXIS_READ(id), QIXIS_READ(arch)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw >= 0x8 && sw <= 0xE) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + /* Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES Reference Clocks: "); + sw = QIXIS_READ(brdcfg[2]); + clock = (sw >> 5) & 7; + printf("Bank1=%sMHz ", freq[clock]); + sw = QIXIS_READ(brdcfg[4]); + clock = (sw >> 6) & 3; + printf("Bank2=%sMHz\n", freq[clock]); + + return 0; +} + +int select_i2c_ch_pca(u8 ch) +{ + int ret; + + /* Selecting proper channel via PCA*/ + ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1); + if (ret) { + printf("PCA: failed to select proper channel.\n"); + return ret; + } + + return 0; +} + +int configure_vsc3316_3308(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned int num_vsc16_con, num_vsc08_con; + u32 serdes1_prtcl, serdes2_prtcl; + int ret; + + serdes1_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + if (!serdes1_prtcl) { + printf("SERDES1 is not enabled\n"); + return 0; + } + serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); + + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + if (!serdes2_prtcl) { + printf("SERDES2 is not enabled\n"); + return 0; + } + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); + + switch (serdes1_prtcl) { + case 0x2a: + case 0x2C: + case 0x2D: + case 0x2E: + /* + * Configuration: + * SERDES: 1 + * Lanes: A,B: SGMII + * Lanes: C,D,E,F,G,H: CPRI + */ + debug("Configuring crossbar to use onboard SGMII PHYs:" + "srds_prctl:%x\n", serdes1_prtcl); + num_vsc16_con = NUM_CON_VSC3316; + /* Configure VSC3316 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3316); + if (!ret) { + ret = vsc3316_config(VSC3316_TX_ADDRESS, + vsc16_tx_sgmii_lane_ab, num_vsc16_con); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_RX_ADDRESS, + vsc16_rx_sgmii_lane_ab, num_vsc16_con); + if (ret) + return ret; + } else { + return ret; + } + break; + +#ifdef CONFIG_PPC_B4420 + case 0x18: + /* + * Configuration: + * SERDES: 1 + * Lanes: A,B,C,D: SGMII + * Lanes: E,F,G,H: CPRI + */ + debug("Configuring crossbar to use onboard SGMII PHYs:" + "srds_prctl:%x\n", serdes1_prtcl); + num_vsc16_con = NUM_CON_VSC3316; + /* Configure VSC3316 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3316); + if (!ret) { + ret = vsc3316_config(VSC3316_TX_ADDRESS, + vsc16_tx_sgmii_lane_cd, num_vsc16_con); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_RX_ADDRESS, + vsc16_rx_sgmii_lane_cd, num_vsc16_con); + if (ret) + return ret; + } else { + return ret; + } + break; +#endif + + case 0x3E: + case 0x0D: + case 0x0E: + case 0x12: + num_vsc16_con = NUM_CON_VSC3316; + /* Configure VSC3316 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3316); + if (!ret) { + ret = vsc3316_config(VSC3316_TX_ADDRESS, + vsc16_tx_sfp, num_vsc16_con); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_RX_ADDRESS, + vsc16_rx_sfp, num_vsc16_con); + if (ret) + return ret; + } else { + return ret; + } + break; + default: + printf("WARNING:VSC crossbars programming not supported for:%x" + " SerDes1 Protocol.\n", serdes1_prtcl); + return -1; + } + + switch (serdes2_prtcl) { + case 0x9E: + case 0x9A: + case 0x98: + case 0xb2: + case 0x49: + case 0x4E: + case 0x8D: + case 0x7A: + num_vsc08_con = NUM_CON_VSC3308; + /* Configure VSC3308 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3308); + if (!ret) { + ret = vsc3308_config(VSC3308_TX_ADDRESS, + vsc08_tx_amc, num_vsc08_con); + if (ret) + return ret; + ret = vsc3308_config(VSC3308_RX_ADDRESS, + vsc08_rx_amc, num_vsc08_con); + if (ret) + return ret; + } else { + return ret; + } + break; + default: + printf("WARNING:VSC crossbars programming not supported for: %x" + " SerDes2 Protocol.\n", serdes2_prtcl); + return -1; + } + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + /* Configure VSC3316 and VSC3308 crossbar switches */ + if (configure_vsc3316_3308()) + printf("VSC:failed to configure VSC3316/3308.\n"); + else + printf("VSC:VSC3316/3308 successfully configured.\n"); + + select_i2c_ch_pca(I2C_CH_DEFAULT); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((sysclk_conf & 0x0C) >> 2) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch (ddrclk_conf & 0x03) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +static int serdes_refclock(u8 sw, u8 sdclk) +{ + unsigned int clock; + int ret = -1; + u8 brdcfg4; + + if (sdclk == 1) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT) + return SRDS_PLLCR0_RFCK_SEL_125; + else + clock = (sw >> 5) & 7; + } else + clock = (sw >> 6) & 3; + + switch (clock) { + case 0: + ret = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + ret = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 2: + ret = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + case 3: + ret = SRDS_PLLCR0_RFCK_SEL_161_13; + break; + case 4: + case 5: + case 6: + ret = SRDS_PLLCR0_RFCK_SEL_122_88; + break; + default: + ret = -1; + break; + } + + return ret; +} + +static const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.13"; + default: + return "122.88"; + } +} + +#define NUM_SRDS_BANKS 2 + +int misc_init_r(void) +{ + u8 sw; + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 actual[NUM_SRDS_BANKS]; + unsigned int i; + int clock; + + sw = QIXIS_READ(brdcfg[2]); + clock = serdes_refclock(sw, 1); + if (clock >= 0) + actual[0] = clock; + else + printf("Warning: SDREFCLK1 switch setting is unsupported\n"); + + sw = QIXIS_READ(brdcfg[4]); + clock = serdes_refclock(sw, 2); + if (clock >= 0) + actual[1] = clock; + else + printf("Warning: SDREFCLK2 switch setting unsupported\n"); + + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 pllcr0 = srds_regs->bank[i].pllcr0; + u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES bank %u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} diff --git a/board/freescale/b4860qds/b4860qds.h b/board/freescale/b4860qds/b4860qds.h new file mode 100644 index 0000000..f290f3c --- /dev/null +++ b/board/freescale/b4860qds/b4860qds.h @@ -0,0 +1,26 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h new file mode 100644 index 0000000..994dec5 --- /dev/null +++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h @@ -0,0 +1,67 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CROSSBAR_CONNECTIONS_H__ +#define __CROSSBAR_CONNECTIONS_H__ + +#define NUM_CON_VSC3316 8 +#define NUM_CON_VSC3308 4 + +static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10}, + {5, 11}, {4, 5}, {2, 6}, {12, 9} }; + +static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1}, + {5, 15}, {4, 14}, {2, 12}, {12, 13} }; + +static const int8_t vsc16_tx_sgmii_lane_ab[8][2] = { {2, 14}, {12, 15}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +#ifdef CONFIG_PPC_B4420 +static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; +#endif +static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9}, + {11, 11}, {5, 10}, {6, 3}, {9, 12} }; + +static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +static const int8_t vsc16_rx_sgmii_lane_ab[8][2] = { {14, 3}, {15, 12}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +#ifdef CONFIG_PPC_B4420 +static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; +#endif + +static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} }; + +static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} }; + +static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} }; + +static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} }; + +#endif diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h new file mode 100644 index 0000000..575b2ae --- /dev/null +++ b/board/freescale/b4860qds/b4860qds_qixis.h @@ -0,0 +1,37 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __B4860QDS_QIXIS_H__ +#define __B4860QDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for B4860QDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* CLK */ +#define QIXIS_CLK_66 0x0 +#define QIXIS_CLK_100 0x1 +#define QIXIS_CLK_125 0x2 +#define QIXIS_CLK_133 0x3 + +#define QIXIS_SRDS1CLK_122 0x5a +#define QIXIS_SRDS1CLK_125 0x5e +#endif diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c new file mode 100644 index 0000000..dd4c0f6 --- /dev/null +++ b/board/freescale/b4860qds/ddr.c @@ -0,0 +1,190 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 or later as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 2147483648u, + .capacity = 4294967296u, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 1, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, /* ECC */ + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1071, + .caslat_X = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ + .tAA_ps = 13910, + .tWR_ps = 15000, + .tRCD_ps = 13910, + .tRRD_ps = 6000, + .tRP_ps = 13910, + .tRAS_ps = 34000, + .tRC_ps = 48910, + .tRFC_ps = 260000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 35000, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "RAW timing DDR"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +}; + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | + */ + {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, + {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, + {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, + {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, + {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, + {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->twoT_en = pbsp_highest->force_2T; + } else { + panic("DIMM is not supported by this board"); + } +found: + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c new file mode 100644 index 0000000..68e2725 --- /dev/null +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -0,0 +1,338 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Author: Sandeep Kumar Singh <sandeep@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */ + +/* + * This file handles the board muxing between the Fman Ethernet MACs and + * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII + * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board. + * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only + * one Fman device on B4860. The SERDES configuration is used to determine + * where the SGMII and XAUI cards exist, and also which Fman MACs are routed + * to which PHYs. So for a given Fman MAC, there is one and only PHY it + * connects to. MACs cannot be routed to PHYs dynamically. This configuration + * is done at boot time by reading SERDES protocol from RCW. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/fsl_serdes.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <fdt_support.h> +#include <asm/fsl_dtsec.h> + +#include "../common/ngpixis.h" +#include "../common/fman.h" +#include "../common/qixis.h" +#include "b4860qds_qixis.h" + +#define EMI_NONE 0xFFFFFFFF + +#ifdef CONFIG_FMAN_ENET + +/* + * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that + * lane at index is mapped to slot number n. A value of '0' will mean + * that the mapping must be determined dynamically, or that the lane maps to + * something other than a board slot + */ +static u8 lane_to_slot[] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0 +}; + +/* + * This function initializes the lane_to_slot[] array. It reads RCW to check + * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes + * lane_to_slot[] accordingly + */ +static void initialize_lane_to_slot(void) +{ + unsigned int serdes2_prtcl; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + debug("Initializing lane to slot: Serdes2 protocol: %x\n", + serdes2_prtcl); + + switch (serdes2_prtcl) { + case 0x18: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B,C,D: SGMII + * Lanes: E,F: Aur + * Lanes: G,H: SRIO + */ + case 0x91: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B: SGMII + * Lanes: C,D: SRIO2 + * Lanes: E,F,G,H: XAUI2 + */ + case 0x93: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B,C,D: SGMII + * Lanes: E,F,G,H: XAUI2 + */ + case 0x98: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B,C,D: XAUI2 + * Lanes: E,F,G,H: XAUI2 + */ + case 0x9a: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B: PCI + * Lanes: C,D: SGMII + * Lanes: E,F,G,H: XAUI2 + */ + case 0x9e: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B,C,D: PCI + * Lanes: E,F,G,H: XAUI2 + */ + case 0xb2: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B,C,D: PCI + * Lanes: E,F: SGMII 3&4 + * Lanes: G,H: XFI + */ + case 0xc2: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B: SGMII + * Lanes: C,D: SRIO2 + * Lanes: E,F,G,H: XAUI2 + */ + lane_to_slot[12] = 2; + lane_to_slot[13] = lane_to_slot[12]; + lane_to_slot[14] = lane_to_slot[12]; + lane_to_slot[15] = lane_to_slot[12]; + break; + + default: + printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", + serdes2_prtcl); + break; + } + return; +} + +#endif /* #ifdef CONFIG_FMAN_ENET */ + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + struct memac_mdio_info tg_memac_mdio_info; + unsigned int i; + unsigned int serdes1_prtcl, serdes2_prtcl; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes1_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + if (!serdes1_prtcl) { + printf("SERDES1 is not enabled\n"); + return 0; + } + serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); + + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + if (!serdes2_prtcl) { + printf("SERDES2 is not enabled\n"); + return 0; + } + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); + + printf("Initializing Fman\n"); + + initialize_lane_to_slot(); + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + tg_memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the real 10G MDIO bus */ + fm_memac_mdio_init(bis, &tg_memac_mdio_info); + + /* + * Program the two on board DTSEC PHY addresses assuming that they are + * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and + * 6 to on board SGMII phys + */ + fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + + switch (serdes1_prtcl) { + case 0x2a: + /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ + debug("Setting phy addresses for FM1_DTSEC5: %x and" + "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + /* Fixing Serdes clock by programming FPGA register */ + QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); + fm_info_set_phy_address(FM1_DTSEC5, + CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, + CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + break; +#ifdef CONFIG_PPC_B4420 + case 0x18: + /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ + debug("Setting phy addresses for FM1_DTSEC3: %x and" + "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + /* Fixing Serdes clock by programming FPGA register */ + QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + break; +#endif + default: + printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + break; + } + switch (serdes2_prtcl) { + case 0x18: + debug("Setting phy addresses on SGMII Riser card for" + "FM1_DTSEC ports: \n"); + fm_info_set_phy_address(FM1_DTSEC1, + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR); + break; + case 0x49: + debug("Setting phy addresses on SGMII Riser card for" + "FM1_DTSEC ports: \n"); + fm_info_set_phy_address(FM1_DTSEC1, + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); + break; + case 0x8d: + case 0xb2: + debug("Setting phy addresses on SGMII Riser card for" + "FM1_DTSEC ports: \n"); + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); + break; + default: + printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", + serdes2_prtcl); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + } + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + int phy; + char alias[32]; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + phy = fm_info_get_phy_address(port); + + sprintf(alias, "phy_sgmii_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i; + char alias[32]; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_NONE: + sprintf(alias, "ethernet%u", i); + fdt_status_disabled_by_alias(fdt, alias); + break; + default: + break; + } + } +} diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c new file mode 100644 index 0000000..4142e01 --- /dev/null +++ b/board/freescale/b4860qds/law.c @@ -0,0 +1,44 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/b4860qds/pci.c b/board/freescale/b4860qds/pci.c new file mode 100644 index 0000000..b130d13 --- /dev/null +++ b/board/freescale/b4860qds/pci.c @@ -0,0 +1,39 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c new file mode 100644 index 0000000..373cb78 --- /dev/null +++ b/board/freescale/b4860qds/tlb.c @@ -0,0 +1,127 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_64K, 1), +#endif + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_4K, 1), + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); |