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-rw-r--r--board/freescale/m5329evb/nand.c42
-rw-r--r--board/freescale/mpc8313erdb/config.mk6
-rw-r--r--board/freescale/mpc8313erdb/mpc8313erdb.c32
-rw-r--r--board/freescale/mpc8313erdb/sdram.c5
-rw-r--r--board/freescale/mpc8540ads/u-boot.lds16
-rw-r--r--board/freescale/mpc8541cds/u-boot.lds16
-rw-r--r--board/freescale/mpc8544ds/u-boot.lds16
-rw-r--r--board/freescale/mpc8548cds/u-boot.lds16
-rw-r--r--board/freescale/mpc8555cds/u-boot.lds16
-rw-r--r--board/freescale/mpc8560ads/u-boot.lds16
-rw-r--r--board/freescale/mpc8568mds/u-boot.lds16
-rw-r--r--board/freescale/mx31ads/Makefile47
-rw-r--r--board/freescale/mx31ads/config.mk1
-rw-r--r--board/freescale/mx31ads/lowlevel_init.S281
-rw-r--r--board/freescale/mx31ads/mx31ads.c106
-rw-r--r--board/freescale/mx31ads/u-boot.lds70
16 files changed, 640 insertions, 62 deletions
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 344a614..f84912e 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -40,36 +40,26 @@ DECLARE_GLOBAL_DATA_PTR;
#define SET_ALE 0x08
#define CLR_ALE ~SET_ALE
-static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd)
+static void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtdinfo->priv;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+/* volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; TODO: handle wp */
u32 nand_baseaddr = (u32) this->IO_ADDR_W;
- switch (cmd) {
- case NAND_CTL_SETNCE:
- case NAND_CTL_CLRNCE:
- break;
- case NAND_CTL_SETCLE:
- nand_baseaddr |= SET_CLE;
- break;
- case NAND_CTL_CLRCLE:
- nand_baseaddr &= CLR_CLE;
- break;
- case NAND_CTL_SETALE:
- nand_baseaddr |= SET_ALE;
- break;
- case NAND_CTL_CLRALE:
- nand_baseaddr |= CLR_ALE;
- break;
- case NAND_CTL_SETWP:
- fbcs->csmr2 |= FBCS_CSMR_WP;
- break;
- case NAND_CTL_CLRWP:
- fbcs->csmr2 &= ~FBCS_CSMR_WP;
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if ( ctrl & NAND_CLE )
+ nand_baseaddr |= SET_CLE;
+ else
+ nand_baseaddr &= CLR_CLE;
+ if ( ctrl & NAND_ALE )
+ nand_baseaddr |= SET_ALE;
+ else
+ nand_baseaddr &= CLR_ALE;
}
this->IO_ADDR_W = (void __iomem *)(nand_baseaddr);
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static void nand_write_byte(struct mtd_info *mtdinfo, u_char byte)
@@ -103,8 +93,8 @@ int board_nand_init(struct nand_chip *nand)
gpio->podr_timer = 0;
nand->chip_delay = 50;
- nand->eccmode = NAND_ECC_SOFT;
- nand->hwcontrol = nand_hwcontrol;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->cmd_ctrl = nand_hwcontrol;
nand->read_byte = nand_read_byte;
nand->write_byte = nand_write_byte;
nand->dev_ready = nand_dev_ready;
diff --git a/board/freescale/mpc8313erdb/config.mk b/board/freescale/mpc8313erdb/config.mk
index f768264..fd72a14 100644
--- a/board/freescale/mpc8313erdb/config.mk
+++ b/board/freescale/mpc8313erdb/config.mk
@@ -1 +1,7 @@
+ifndef NAND_SPL
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+endif
+
+ifndef TEXT_BASE
TEXT_BASE = 0xFE000000
+endif
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 7cbdb7b..ebb703d 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -29,6 +29,8 @@
#include <pci.h>
#include <mpc83xx.h>
#include <vsc7385.h>
+#include <ns16550.h>
+#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -50,6 +52,7 @@ int checkboard(void)
return 0;
}
+#ifndef CONFIG_NAND_SPL
static struct pci_region pci_regions[] = {
{
bus_start: CFG_PCI1_MEM_BASE,
@@ -128,3 +131,32 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
}
#endif
+#else /* CONFIG_NAND_SPL */
+void board_init_f(ulong bootflag)
+{
+ board_early_init_f();
+ NS16550_init((NS16550_t)(CFG_IMMR + 0x4500),
+ CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+ puts("NAND boot... ");
+ init_timebase();
+ initdram(0);
+ relocate_code(CFG_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+ CFG_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+ nand_boot();
+}
+
+void putc(char c)
+{
+ if (gd->flags & GD_FLG_SILENT)
+ return;
+
+ if (c == '\n')
+ NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), '\r');
+
+ NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), c);
+}
+#endif
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index afd8b9d..3a6347f 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -58,8 +58,10 @@ static void resume_from_sleep(void)
*/
static long fixed_sdram(void)
{
- volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+
+#ifndef CFG_RAMBOOT
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
u32 msize_log2 = __ilog2(msize);
im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
@@ -100,6 +102,7 @@ static long fixed_sdram(void)
/* enable DDR controller */
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
+#endif
return msize;
}
diff --git a/board/freescale/mpc8540ads/u-boot.lds b/board/freescale/mpc8540ads/u-boot.lds
index 0e4f5a2..515d320 100644
--- a/board/freescale/mpc8540ads/u-boot.lds
+++ b/board/freescale/mpc8540ads/u-boot.lds
@@ -26,6 +26,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
@@ -57,7 +63,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
- }
+ } :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@@ -66,7 +72,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
- }
+ } :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@@ -118,12 +124,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
- } = 0xffff
+ } :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
- } = 0xffff
+ } :text = 0xffff
. = ADDR(.text) + 0x80000;
@@ -134,7 +140,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
- }
+ } :bss
. = ALIGN(4);
_end = . ;
diff --git a/board/freescale/mpc8541cds/u-boot.lds b/board/freescale/mpc8541cds/u-boot.lds
index 1c583de..d728d8b 100644
--- a/board/freescale/mpc8541cds/u-boot.lds
+++ b/board/freescale/mpc8541cds/u-boot.lds
@@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
@@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
- }
+ } :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
- }
+ } :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
- } = 0xffff
+ } :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
- } = 0xffff
+ } :text = 0xffff
. = ADDR(.text) + 0x80000;
@@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
- }
+ } :bss
. = ALIGN(4);
_end = . ;
diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds
index 500e647..a05ece5 100644
--- a/board/freescale/mpc8544ds/u-boot.lds
+++ b/board/freescale/mpc8544ds/u-boot.lds
@@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
@@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
- }
+ } :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
- }
+ } :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
- } = 0xffff
+ } :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
- } = 0xffff
+ } :text = 0xffff
. = ADDR(.text) + 0x80000;
@@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
- }
+ } :bss
. = ALIGN(4);
_end = . ;
diff --git a/board/freescale/mpc8548cds/u-boot.lds b/board/freescale/mpc8548cds/u-boot.lds
index 6b93395..d4a2f72 100644
--- a/board/freescale/mpc8548cds/u-boot.lds
+++ b/board/freescale/mpc8548cds/u-boot.lds
@@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
@@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
- }
+ } :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
- }
+ } :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
- } = 0xffff
+ } :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
- } = 0xffff
+ } :text = 0xffff
. = ADDR(.text) + 0x80000;
@@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
- }
+ } :bss
. = ALIGN(4);
_end = . ;
diff --git a/board/freescale/mpc8555cds/u-boot.lds b/board/freescale/mpc8555cds/u-boot.lds
index a18b3a7..11885e8 100644
--- a/board/freescale/mpc8555cds/u-boot.lds
+++ b/board/freescale/mpc8555cds/u-boot.lds
@@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
@@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
- }
+ } :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
- }
+ } :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
- } = 0xffff
+ } :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
- } = 0xffff
+ } :text = 0xffff
. = ADDR(.text) + 0x80000;
@@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
- }
+ } :bss
. = ALIGN(4);
_end = . ;
diff --git a/board/freescale/mpc8560ads/u-boot.lds b/board/freescale/mpc8560ads/u-boot.lds
index 0e4f5a2..515d320 100644
--- a/board/freescale/mpc8560ads/u-boot.lds
+++ b/board/freescale/mpc8560ads/u-boot.lds
@@ -26,6 +26,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
@@ -57,7 +63,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
- }
+ } :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@@ -66,7 +72,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
- }
+ } :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@@ -118,12 +124,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
- } = 0xffff
+ } :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
- } = 0xffff
+ } :text = 0xffff
. = ADDR(.text) + 0x80000;
@@ -134,7 +140,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
- }
+ } :bss
. = ALIGN(4);
_end = . ;
diff --git a/board/freescale/mpc8568mds/u-boot.lds b/board/freescale/mpc8568mds/u-boot.lds
index 9d245e4..ad96410 100644
--- a/board/freescale/mpc8568mds/u-boot.lds
+++ b/board/freescale/mpc8568mds/u-boot.lds
@@ -23,6 +23,12 @@
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
@@ -54,7 +60,7 @@ SECTIONS
*(.text)
*(.fixup)
*(.got1)
- }
+ } :text
_etext = .;
PROVIDE (etext = .);
.rodata :
@@ -63,7 +69,7 @@ SECTIONS
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
- }
+ } :text
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
@@ -115,12 +121,12 @@ SECTIONS
.bootpg ADDR(.text) + 0x7f000 :
{
cpu/mpc85xx/start.o (.bootpg)
- } = 0xffff
+ } :text = 0xffff
.resetvec ADDR(.text) + 0x7fffc :
{
*(.resetvec)
- } = 0xffff
+ } :text = 0xffff
. = ADDR(.text) + 0x80000;
@@ -131,7 +137,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
- }
+ } :bss
. = ALIGN(4);
_end = . ;
diff --git a/board/freescale/mx31ads/Makefile b/board/freescale/mx31ads/Makefile
new file mode 100644
index 0000000..a12f391
--- /dev/null
+++ b/board/freescale/mx31ads/Makefile
@@ -0,0 +1,47 @@
+#
+# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := mx31ads.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx31ads/config.mk b/board/freescale/mx31ads/config.mk
new file mode 100644
index 0000000..d34dc02
--- /dev/null
+++ b/board/freescale/mx31ads/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x87f00000
diff --git a/board/freescale/mx31ads/lowlevel_init.S b/board/freescale/mx31ads/lowlevel_init.S
new file mode 100644
index 0000000..e166058
--- /dev/null
+++ b/board/freescale/mx31ads/lowlevel_init.S
@@ -0,0 +1,281 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/mx31-regs.h>
+
+.macro REG reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ str r3, [r2]
+.endm
+
+.macro REG8 reg, val
+ ldr r2, =\reg
+ ldr r3, =\val
+ strb r3, [r2]
+.endm
+
+.macro DELAY loops
+ ldr r2, =\loops
+1:
+ subs r2, r2, #1
+ nop
+ bcs 1b
+.endm
+
+/* RedBoot: AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =0x43F00000
+ ldr r1, =0x77777777
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, =0x53F00000
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ ldr r0, =0x43F00000
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+
+ ldr r0, =0x53F00000
+ ldr r1, =0x0
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ ldr r1, [r0, #0x50]
+ and r1, r1, #0x00FFFFFF
+ str r1, [r0, #0x50]
+.endm /* init_aips */
+
+/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+ ldr r0, =0x43F04000
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, =0x00302154
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =0x10
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =0x0
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+.endm /* init_max */
+
+/* RedBoot: M3IF setup */
+.macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, =0xB8003000
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ ldr r0, =0x00000040
+ str r0, [r1] /* M3IF control reg */
+.endm /* init_m3if */
+
+/* RedBoot: To support 133MHz DDR */
+.macro init_drive_strength
+ /*
+ * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
+ * in SW_PAD_CTL registers
+ */
+
+ /* SDCLK */
+ ldr r1, =0x43FAC200
+ ldr r0, [r1, #0x6C]
+ bic r0, r0, #(1 << 12)
+ str r0, [r1, #0x6C]
+
+ /* CAS */
+ ldr r0, [r1, #0x70]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x70]
+
+ /* RAS */
+ ldr r0, [r1, #0x74]
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x74]
+
+ /* CS2 (CSD0) */
+ ldr r0, [r1, #0x7C]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x7C]
+
+ /* DQM3 */
+ ldr r0, [r1, #0x84]
+ bic r0, r0, #(1 << 22)
+ str r0, [r1, #0x84]
+
+ /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
+ ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
+pad_loop:
+ ldr r0, [r1, #0x88]
+ bic r0, r0, #(1 << 22)
+ bic r0, r0, #(1 << 12)
+ bic r0, r0, #(1 << 2)
+ str r0, [r1, #0x88]
+ add r1, r1, #4
+ subs r2, r2, #0x1
+ bne pad_loop
+.endm /* init_drive_strength */
+
+/* CPLD on CS4 setup */
+.macro init_cs4
+ ldr r0, =WEIM_BASE
+ ldr r1, =0x0000D843
+ str r1, [r0, #0x40]
+ ldr r1, =0x22252521
+ str r1, [r0, #0x44]
+ ldr r1, =0x22220A00
+ str r1, [r0, #0x48]
+.endm /* init_cs4 */
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Redboot initializes very early AIPS, what for?
+ * Then it also initializes Multi-Layer AHB Crossbar Switch,
+ * M3IF */
+ /* Also setup the Peripheral Port Remap register inside the core */
+ ldr r0, =0x40000015 /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ init_drive_strength
+
+ init_cs4
+
+ /* Image Processing Unit: */
+ /* Too early to switch display on? */
+ REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */
+ /* Clock Control Module: */
+ REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
+
+ DELAY 0x40000
+
+ REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
+ REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */
+
+ /* PBC CPLD on CS4 */
+ mov r1, #CS4_BASE
+ ldrh r1, [r1, #0x2]
+ /* Is 27MHz switch set? */
+ ands r1, r1, #0x10
+
+ /* 532-133-66.5 */
+ ldr r0, =CCM_BASE
+ ldr r1, =0xFF871D58
+ /* PDR0 */
+ str r1, [r0, #0x4]
+ ldreq r1, MPCTL_PARAM_532
+ ldrne r1, MPCTL_PARAM_532_27
+ /* MPCTL */
+ str r1, [r0, #0x10]
+
+ /* Set UPLL=240MHz, USB=60MHz */
+ ldr r1, =0x49FCFE7F
+ /* PDR1 */
+ str r1, [r0, #0x8]
+ ldreq r1, UPCTL_PARAM_240
+ ldrne r1, UPCTL_PARAM_240_27
+ /* UPCTL */
+ str r1, [r0, #0x14]
+ /* default CLKO to 1/8 of the ARM core */
+ mov r1, #0x000002C0
+ add r1, r1, #0x00000006
+ /* COSR */
+ str r1, [r0, #0x1c]
+
+ /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
+/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
+
+ /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
+/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
+ /* Default: 1, 4, 12, 1 */
+ REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+ /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
+ REG 0xB8001010, 0x00000004
+ REG 0xB8001004, 0x006ac73a
+ REG 0xB8001000, 0x92100000
+ REG 0x80000f00, 0x12344321
+ REG 0xB8001000, 0xa2100000
+ REG 0x80000000, 0x12344321
+ REG 0x80000000, 0x12344321
+ REG 0xB8001000, 0xb2100000
+ REG8 0x80000033, 0xda
+ REG8 0x81000000, 0xff
+ REG 0xB8001000, 0x82226080
+ REG 0x80000000, 0xDEADBEEF
+ REG 0xB8001010, 0x0000000c
+
+ mov pc, lr
+
+MPCTL_PARAM_532:
+ .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
+MPCTL_PARAM_532_27:
+ .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0))
+UPCTL_PARAM_240:
+ .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0))
+UPCTL_PARAM_240_27:
+ .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0))
diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c
new file mode 100644
index 0000000..c24c47c
--- /dev/null
+++ b/board/freescale/mx31ads/mx31ads.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int board_init (void)
+{
+ int i;
+
+ /* CS0: Nor Flash */
+ /*
+ * CS0L and CS0A values are from the RedBoot sources by Freescale
+ * and are also equal to those used by Sascha Hauer for the Phytec
+ * i.MX31 board. CS0U is just a slightly optimized hardware default:
+ * the only non-zero field "Wait State Control" is set to half the
+ * default value.
+ */
+ __REG(CSCR_U(0)) = 0x00000f00;
+ __REG(CSCR_L(0)) = 0x10000D03;
+ __REG(CSCR_A(0)) = 0x00720900;
+
+ /* setup pins for UART1 */
+ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
+ mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
+ mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
+ mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
+
+ /* SPI2 */
+ mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
+ mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
+ mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
+ mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
+ mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
+ mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
+ mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
+
+ /* start SPI2 clock */
+ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+
+ /* PBC setup */
+ /* Enable UART transceivers also reset the Ethernet/external UART */
+ readw(CS4_BASE + 4);
+
+ writew(0x8023, CS4_BASE + 4);
+
+ /* RedBoot also has an empty loop with 100000 iterations here -
+ * clock doesn't run yet */
+ for (i = 0; i < 100000; i++)
+ ;
+
+ /* Clear the reset, toggle the LEDs */
+ writew(0xDF, CS4_BASE + 6);
+
+ /* clock still doesn't run */
+ for (i = 0; i < 100000; i++)
+ ;
+
+ /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
+ readb(CS4_BASE + 8);
+ readb(CS4_BASE + 7);
+ readb(CS4_BASE + 8);
+ readb(CS4_BASE + 7);
+
+ gd->bd->bi_arch_number = MACH_TYPE_MX31ADS; /* board id for linux */
+ gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ printf("Board: MX31ADS\n");
+ return 0;
+}
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
new file mode 100644
index 0000000..c379460
--- /dev/null
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -0,0 +1,70 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/arm1136/start.o (.text)
+ board/freescale/mx31ads/libmx31ads.a (.text)
+ lib_arm/libarm.a (.text)
+ net/libnet.a (.text)
+ drivers/mtd/libmtd.a (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/environment.o(.text)
+
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
generated by cgit v1.1 at 2024-12-22 08:14:17 +0000