diff options
Diffstat (limited to 'board/freescale/t1040qds')
-rw-r--r-- | board/freescale/t1040qds/ddr.c | 19 | ||||
-rw-r--r-- | board/freescale/t1040qds/eth.c | 93 | ||||
-rw-r--r-- | board/freescale/t1040qds/t1040qds.c | 23 |
3 files changed, 123 insertions, 12 deletions
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 43f952f..8240240 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -11,6 +11,7 @@ #include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> #include <asm/fsl_law.h> +#include <asm/mpc85xx_gpio.h> #include "ddr.h" DECLARE_GLOBAL_DATA_PTR; @@ -100,6 +101,19 @@ found: #endif } +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void) +{ + void __iomem *qixis_base = (void *)QIXIS_BASE; + + /* does not provide HW signals for power management */ + clrbits_8(qixis_base + 0x21, 0x2); + /* Disable MCKE isolation */ + gpio_set_value(2, 0); + udelay(1); +} +#endif + phys_size_t initdram(int board_type) { phys_size_t dram_size; @@ -112,5 +126,10 @@ phys_size_t initdram(int board_type) dram_size *= 0x100000; puts(" DDR: "); + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + return dram_size; } diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c index 06d9086..8c82934 100644 --- a/board/freescale/t1040qds/eth.c +++ b/board/freescale/t1040qds/eth.c @@ -18,6 +18,7 @@ #include <fsl_mdio.h> #include <malloc.h> #include <asm/fsl_dtsec.h> +#include <vsc9953.h> #include "../common/fman.h" #include "../common/qixis.h" @@ -216,6 +217,7 @@ static void initialize_lane_to_slot(void) lane_to_slot[1] = 7; lane_to_slot[2] = 7; lane_to_slot[3] = 7; + lane_to_slot[6] = 7; lane_to_slot[7] = 7; break; case 0x8d: @@ -438,6 +440,12 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_FMAN_ENET struct memac_mdio_info memac_mdio_info; unsigned int i; +#ifdef CONFIG_VSC9953 + int lane; + int phy_addr; + phy_interface_t phy_int; + struct mii_dev *bus; +#endif printf("Initializing Fman\n"); set_brdcfg9_for_gtx_clk(); @@ -477,6 +485,7 @@ int board_eth_init(bd_t *bis) for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { switch (fm_info_get_enet_if(i)) { case PHY_INTERFACE_MODE_QSGMII: + fm_info_set_mdio(i, NULL); break; case PHY_INTERFACE_MODE_SGMII: t1040_handle_phy_interface_sgmii(i); @@ -491,6 +500,90 @@ int board_eth_init(bd_t *bis) } } +#ifdef CONFIG_VSC9953 + for (i = 0; i < VSC9953_MAX_PORTS; i++) { + lane = -1; + phy_addr = 0; + phy_int = PHY_INTERFACE_MODE_NONE; + switch (i) { + case 0: + case 1: + case 2: + case 3: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A); + /* PHYs connected over QSGMII */ + if (lane >= 0) { + phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + + i; + phy_int = PHY_INTERFACE_MODE_QSGMII; + break; + } + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_SW1_MAC1 + i); + + if (lane < 0) + break; + + /* PHYs connected over QSGMII */ + if (i != 3 || lane_to_slot[lane] == 7) + phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + + i; + else + phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR; + phy_int = PHY_INTERFACE_MODE_SGMII; + break; + case 4: + case 5: + case 6: + case 7: + lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B); + /* PHYs connected over QSGMII */ + if (lane >= 0) { + phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + + i - 4; + phy_int = PHY_INTERFACE_MODE_QSGMII; + break; + } + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_SW1_MAC1 + i); + /* PHYs connected over SGMII */ + if (lane >= 0) { + phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + + i - 3; + phy_int = PHY_INTERFACE_MODE_SGMII; + } + break; + case 8: + if (serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1) < 0) + /* FM1@DTSEC1 is connected to SW1@PORT8 */ + vsc9953_port_enable(i); + break; + case 9: + if (serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC2) < 0) { + /* Enable L2 On MAC2 using SCFG */ + struct ccsr_scfg *scfg = (struct ccsr_scfg *) + CONFIG_SYS_MPC85xx_SCFG; + + out_be32(&scfg->esgmiiselcr, + in_be32(&scfg->esgmiiselcr) | + (0x80000000)); + vsc9953_port_enable(i); + } + break; + } + + if (lane >= 0) { + bus = mii_dev_for_muxval(lane_to_slot[lane]); + vsc9953_port_info_set_mdio(i, bus); + vsc9953_port_enable(i); + } + vsc9953_port_info_set_phy_address(i, phy_addr); + vsc9953_port_info_set_phy_int(i, phy_int); + } + +#endif cpu_eth_init(bis); #endif diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index 13285be..eaca57f 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -19,8 +19,8 @@ #include <asm/fsl_liodn.h> #include <fm_eth.h> #include <hwconfig.h> -#include <asm/mpc85xx_gpio.h> +#include "../common/sleep.h" #include "../common/qixis.h" #include "t1040qds.h" #include "t1040qds_qixis.h" @@ -115,6 +115,16 @@ static void qe_board_setup(void) } } +int board_early_init_f(void) +{ +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + return 0; +} + int board_early_init_r(void) { #ifdef CONFIG_SYS_FLASH_BASE @@ -281,14 +291,3 @@ int board_need_mem_reset(void) { return 1; } - -#ifdef CONFIG_DEEP_SLEEP -void board_mem_sleep_setup(void) -{ - /* does not provide HW signals for power management */ - QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2)); - /* Disable MCKE isolation */ - gpio_set_value(2, 0); - udelay(1); -} -#endif |