diff options
Diffstat (limited to 'board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c')
-rw-r--r-- | board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c b/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c index 0751829..765d5cc 100644 --- a/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c +++ b/board/freescale/mx6ul_14x14_ddr3_arm2/mx6ul_14x14_ddr3_arm2.c @@ -339,10 +339,25 @@ static void eimnor_cs_setup(void) static void setup_eimnor(void) { + if (check_module_fused(MX6_MODULE_EIM)) { + printf("WEIM@0x%x is fused, disable it\n", WEIM_BASE_ADDR); + return; + } + imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads)); eimnor_cs_setup(); } + +int board_flash_wp_on(void) +{ + if (check_module_fused(MX6_MODULE_EIM)) { + return 1; /* Skip flash init */ + } + + return 0; +} + #endif #ifdef CONFIG_FEC_MXC @@ -489,11 +504,17 @@ int mmc_get_env_devno(void) /* BOOT_CFG2[3] and BOOT_CFG2[4] */ dev_no = (soc_sbmr & 0x00001800) >> 11; + if (dev_no == 1 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) + dev_no = 0; + return dev_no; } int mmc_map_to_kernel_blk(int dev_no) { + if (dev_no == 0 && mx6_esdhc_fused(USDHC1_BASE_ADDR)) + dev_no = 1; + return dev_no; } @@ -532,7 +553,7 @@ int board_mmc_init(bd_t *bis) */ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { switch (i) { - case 0: + case 0: #ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK imx_iomux_v3_setup_multiple_pads( usdhc1_emmc_pads, ARRAY_SIZE(usdhc1_emmc_pads)); @@ -735,6 +756,10 @@ static int setup_fec(int fec_id) int ret; if (0 == fec_id) { + if (check_module_fused(MX6_MODULE_ENET1)) { + return -1; + } + /* * Use 50M anatop loopback REF_CLK1 for ENET1, * clear gpr1[13], set gpr1[17] @@ -746,6 +771,10 @@ static int setup_fec(int fec_id) return ret; } else { + if (check_module_fused(MX6_MODULE_ENET2)) { + return -1; + } + /* clk from phy, set gpr1[14], clear gpr1[18]*/ clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK); |