diff options
Diffstat (limited to 'board/freescale/mx6sabresd/mx6sabresd.c')
| -rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 804 |
1 files changed, 488 insertions, 316 deletions
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 562355d..0a6c29e 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. * * Author: Fabio Estevam <fabio.estevam@freescale.com> * @@ -30,12 +30,22 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <i2c.h> +#include <ipu_pixfmt.h> +#include <linux/fb.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> #include "../common/pfuze.h" #include <asm/arch/mx6-ddr.h> #include <usb.h> +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +#include <lcd.h> +#include <mxc_epdc_fb.h> +#endif +#ifdef CONFIG_CMD_SATA +#include <asm/imx-common/sata.h> +#endif + DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -56,6 +66,9 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + #define I2C_PMIC 1 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -146,6 +159,7 @@ static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +#ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -153,6 +167,17 @@ static iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; +} +#endif + static iomux_v3_cfg_t const rgb_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -205,11 +230,6 @@ static struct i2c_pads_info i2c_pad_info1 = { } }; -static void setup_spi(void) -{ - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); -} - iomux_v3_cfg_t const pcie_pads[] = { MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ @@ -228,49 +248,49 @@ iomux_v3_cfg_t const di0_pads[] = { #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) static iomux_v3_cfg_t const epdc_enable_pads[] = { - MX6_PAD_EIM_A16__EPDC_SDDO_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_DA10__EPDC_SDDO_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_DA12__EPDC_SDDO_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_DA11__EPDC_SDDO_3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_LBA__EPDC_SDDO_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_EB2__EPDC_SDDO_5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_CS0__EPDC_SDDO_6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_RW__EPDC_SDDO_7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_D31__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_DA2__EPDC_BDR_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_DA4__EPDC_SDCE_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_DA5__EPDC_SDCE_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), - MX6_PAD_EIM_DA6__EPDC_SDCE_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), }; static iomux_v3_cfg_t const epdc_disable_pads[] = { - MX6_PAD_EIM_A16__GPIO_2_22, - MX6_PAD_EIM_DA10__GPIO_3_10, - MX6_PAD_EIM_DA12__GPIO_3_12, - MX6_PAD_EIM_DA11__GPIO_3_11, - MX6_PAD_EIM_LBA__GPIO_2_27, - MX6_PAD_EIM_EB2__GPIO_2_30, - MX6_PAD_EIM_CS0__GPIO_2_23, - MX6_PAD_EIM_RW__GPIO_2_26, - MX6_PAD_EIM_A21__GPIO_2_17, - MX6_PAD_EIM_A22__GPIO_2_16, - MX6_PAD_EIM_A23__GPIO_6_6, - MX6_PAD_EIM_A24__GPIO_5_4, - MX6_PAD_EIM_D31__GPIO_3_31, - MX6_PAD_EIM_D27__GPIO_3_27, - MX6_PAD_EIM_DA1__GPIO_3_1, - MX6_PAD_EIM_EB1__GPIO_2_29, - MX6_PAD_EIM_DA2__GPIO_3_2, - MX6_PAD_EIM_DA4__GPIO_3_4, - MX6_PAD_EIM_DA5__GPIO_3_5, - MX6_PAD_EIM_DA6__GPIO_3_6, + MX6_PAD_EIM_A16__GPIO2_IO22, + MX6_PAD_EIM_DA10__GPIO3_IO10, + MX6_PAD_EIM_DA12__GPIO3_IO12, + MX6_PAD_EIM_DA11__GPIO3_IO11, + MX6_PAD_EIM_LBA__GPIO2_IO27, + MX6_PAD_EIM_EB2__GPIO2_IO30, + MX6_PAD_EIM_CS0__GPIO2_IO23, + MX6_PAD_EIM_RW__GPIO2_IO26, + MX6_PAD_EIM_A21__GPIO2_IO17, + MX6_PAD_EIM_A22__GPIO2_IO16, + MX6_PAD_EIM_A23__GPIO6_IO06, + MX6_PAD_EIM_A24__GPIO5_IO04, + MX6_PAD_EIM_D31__GPIO3_IO31, + MX6_PAD_EIM_D27__GPIO3_IO27, + MX6_PAD_EIM_DA1__GPIO3_IO01, + MX6_PAD_EIM_EB1__GPIO2_IO29, + MX6_PAD_EIM_DA2__GPIO3_IO02, + MX6_PAD_EIM_DA4__GPIO3_IO04, + MX6_PAD_EIM_DA5__GPIO3_IO05, + MX6_PAD_EIM_DA6__GPIO3_IO06, }; #endif @@ -286,6 +306,35 @@ struct fsl_esdhc_cfg usdhc_cfg[3] = { {USDHC4_BASE_ADDR}, }; +int mmc_get_env_devno(void) +{ + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + u32 dev_no; + u32 bootsel; + + bootsel = (soc_sbmr & 0x000000FF) >> 6 ; + + /* If not boot from sd/mmc, use default value */ + if (bootsel != 1) + return CONFIG_SYS_MMC_ENV_DEV; + + /* BOOT_CFG2[3] and BOOT_CFG2[4] */ + dev_no = (soc_sbmr & 0x00001800) >> 11; + + /* need ubstract 1 to map to the mmc device id + * see the comments in board_mmc_init function + */ + + dev_no--; + + return dev_no; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no + 1; +} + #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) @@ -395,6 +444,306 @@ int board_mmc_init(bd_t *bis) } #endif +int check_mmc_autodetect(void) +{ + char *autodetect_str = getenv("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_devno(); + + if (!check_mmc_autodetect()) + return; + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} + +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +#ifdef CONFIG_SPLASH_SCREEN +extern int mmc_get_env_devno(void); +int setup_splash_img(void) +{ +#ifdef CONFIG_SPLASH_IS_IN_MMC + int mmc_dev = mmc_get_env_devno(); + ulong offset = CONFIG_SPLASH_IMG_OFFSET; + ulong size = CONFIG_SPLASH_IMG_SIZE; + ulong addr = 0; + char *s = NULL; + struct mmc *mmc = find_mmc_device(mmc_dev); + uint blk_start, blk_cnt, n; + + s = getenv("splashimage"); + + if (NULL == s) { + puts("env splashimage not found!\n"); + return -1; + } + addr = simple_strtoul(s, NULL, 16); + + if (!mmc) { + printf("MMC Device %d not found\n", mmc_dev); + return -1; + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return -1; + } + + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; + n = mmc->block_dev.block_read(mmc_dev, blk_start, + blk_cnt, (u_char *)addr); + flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); + + return (n == blk_cnt) ? 0 : -1; +#endif + + return 0; +} +#endif + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 800, + .vl_row = 600, + .vl_pixclock = 26666667, + .vl_left_margin = 8, + .vl_right_margin = 100, + .vl_upper_margin = 4, + .vl_lower_margin = 8, + .vl_hsync = 4, + .vl_vsync = 1, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 419, + .gdsp_offs = 20, + .gdoe_offs = 0, + .gdclk_offs = 5, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* Setup epdc voltage */ + + /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as input */ + gpio_direction_input(IMX_GPIO_NR(2, 21)); + + /* EIM_D17 - GPIO3[17] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_direction_output(IMX_GPIO_NR(3, 17), 1); + + /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_direction_output(IMX_GPIO_NR(3, 20), 1); + + /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_direction_output(IMX_GPIO_NR(2, 20), 1); +} + +int setup_waveform_file(void) +{ +#ifdef CONFIG_WAVEFORM_FILE_IN_MMC + int mmc_dev = mmc_get_env_devno(); + ulong offset = CONFIG_WAVEFORM_FILE_OFFSET; + ulong size = CONFIG_WAVEFORM_FILE_SIZE; + ulong addr = CONFIG_WAVEFORM_BUF_ADDR; + struct mmc *mmc = find_mmc_device(mmc_dev); + uint blk_start, blk_cnt, n; + + if (!mmc) { + printf("MMC Device %d not found\n", mmc_dev); + return -1; + } + + if (mmc_init(mmc)) { + puts("MMC init failed\n"); + return -1; + } + + blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; + blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; + n = mmc->block_dev.block_read(mmc_dev, blk_start, + blk_cnt, (u_char *)addr); + flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); + + return (n == blk_cnt) ? 0 : -1; +#else + return -1; +#endif +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + unsigned int reg; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /*** epdc Maxim PMIC settings ***/ + + /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC VCOM0 - GPIO3[17] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /*** Set pixel clock rates for EPDC ***/ + + /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ + reg = readl(&ccm_regs->cscdr3); + reg &= ~0x7C000; + reg |= (1 << 16) | (1 << 14); + writel(reg, &ccm_regs->cscdr3); + + /* EPDC AXI clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x00C0; + writel(reg, &ccm_regs->CCGR3); + + /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ + reg = readl(&ccm_regs->cscdr2); + reg &= ~0x3FE00; + reg |= (2 << 15) | (5 << 12); + writel(reg, &ccm_regs->cscdr2); + + /* PLL5 enable (defaults to 650) */ + reg = readl(&ccm_regs->analog_pll_video); + reg &= ~((1 << 16) | (1 << 12)); + reg |= (1 << 13); + writel(reg, &ccm_regs->analog_pll_video); + + /* EPDC PIX clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x0C00; + writel(reg, &ccm_regs->CCGR3); + + panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR; + panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR; + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); + + /* Assign fb_base */ + gd->fb_base = CONFIG_FB_BASE; +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 20), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 20), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 21))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 17), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 20), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 17), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 20), 0); +} +#endif + int mx6_rgmii_rework(struct phy_device *phydev) { unsigned short val; @@ -666,272 +1015,6 @@ int board_early_init_f(void) return 0; } -#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) -#ifdef CONFIG_SPLASH_SCREEN -extern int mmc_get_env_devno(void); -int setup_splash_img(void) -{ -#ifdef CONFIG_SPLASH_IS_IN_MMC - int mmc_dev = mmc_get_env_devno(); - ulong offset = CONFIG_SPLASH_IMG_OFFSET; - ulong size = CONFIG_SPLASH_IMG_SIZE; - ulong addr = 0; - char *s = NULL; - struct mmc *mmc = find_mmc_device(mmc_dev); - uint blk_start, blk_cnt, n; - - s = getenv("splashimage"); - - if (NULL == s) { - puts("env splashimage not found!\n"); - return -1; - } - addr = simple_strtoul(s, NULL, 16); - - if (!mmc) { - printf("MMC Device %d not found\n", mmc_dev); - return -1; - } - - if (mmc_init(mmc)) { - puts("MMC init failed\n"); - return -1; - } - - blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; - blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; - n = mmc->block_dev.block_read(mmc_dev, blk_start, - blk_cnt, (u_char *)addr); - flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); - - return (n == blk_cnt) ? 0 : -1; -#endif - - return 0; -} -#endif - -vidinfo_t panel_info = { - .vl_refresh = 85, - .vl_col = 800, - .vl_row = 600, - .vl_pixclock = 26666667, - .vl_left_margin = 8, - .vl_right_margin = 100, - .vl_upper_margin = 4, - .vl_lower_margin = 8, - .vl_hsync = 4, - .vl_vsync = 1, - .vl_sync = 0, - .vl_mode = 0, - .vl_flag = 0, - .vl_bpix = 3, - .cmap = 0, -}; - -struct epdc_timing_params panel_timings = { - .vscan_holdoff = 4, - .sdoed_width = 10, - .sdoed_delay = 20, - .sdoez_width = 10, - .sdoez_delay = 20, - .gdclk_hp_offs = 419, - .gdsp_offs = 20, - .gdoe_offs = 0, - .gdclk_offs = 5, - .num_ce = 1, -}; - -static void setup_epdc_power(void) -{ - /* Setup epdc voltage */ - - /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ - imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO_2_21 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - /* Set as input */ - gpio_direction_input(IMX_GPIO_NR(2, 21)); - - /* EIM_D17 - GPIO3[17] for VCOM control */ - imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO_3_17 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - - /* Set as output */ - gpio_direction_output(IMX_GPIO_NR(3, 17), 1); - - /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ - imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO_3_20 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - /* Set as output */ - gpio_direction_output(IMX_GPIO_NR(3, 20), 1); - - /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ - imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO_2_20 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - /* Set as output */ - gpio_direction_output(IMX_GPIO_NR(2, 20), 1); -} - -int setup_waveform_file(void) -{ -#ifdef CONFIG_WAVEFORM_FILE_IN_MMC - int mmc_dev = mmc_get_env_devno(); - ulong offset = CONFIG_WAVEFORM_FILE_OFFSET; - ulong size = CONFIG_WAVEFORM_FILE_SIZE; - ulong addr = CONFIG_WAVEFORM_BUF_ADDR; - struct mmc *mmc = find_mmc_device(mmc_dev); - uint blk_start, blk_cnt, n; - - if (!mmc) { - printf("MMC Device %d not found\n", mmc_dev); - return -1; - } - - if (mmc_init(mmc)) { - puts("MMC init failed\n"); - return -1; - } - - blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; - blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len; - n = mmc->block_dev.block_read(mmc_dev, blk_start, - blk_cnt, (u_char *)addr); - flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len); - - return (n == blk_cnt) ? 0 : -1; -#else - return -1; -#endif -} - -static void epdc_enable_pins(void) -{ - /* epdc iomux settings */ - imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, - ARRAY_SIZE(epdc_enable_pads)); -} - -static void epdc_disable_pins(void) -{ - /* Configure MUX settings for EPDC pins to GPIO */ - imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, - ARRAY_SIZE(epdc_disable_pads)); -} - -static void setup_epdc(void) -{ - unsigned int reg; - - /*** epdc Maxim PMIC settings ***/ - - /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */ - imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO_2_21 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - - /* EPDC VCOM0 - GPIO3[17] for VCOM control */ - imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO_3_17 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - - /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */ - imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO_3_20 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - - /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ - imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO_2_20 | - MUX_PAD_CTRL(EPDC_PAD_CTRL)); - - /*** Set pixel clock rates for EPDC ***/ - - /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ - reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR3); - reg &= ~0x7C000; - reg |= (1 << 16) | (1 << 14); - writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR3); - - /* EPDC AXI clk enable */ - reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3); - reg |= 0x00C0; - writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3); - - /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ - reg = readl(CCM_BASE_ADDR + CLKCTL_CSCDR2); - reg &= ~0x3FE00; - reg |= (2 << 15) | (5 << 12); - writel(reg, CCM_BASE_ADDR + CLKCTL_CSCDR2); - - /* PLL5 enable (defaults to 650) */ - reg = readl(ANATOP_BASE_ADDR + ANATOP_PLL_VIDEO); - reg &= ~((1 << 16) | (1 << 12)); - reg |= (1 << 13); - writel(reg, ANATOP_BASE_ADDR + ANATOP_PLL_VIDEO); - - /* EPDC PIX clk enable */ - reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3); - reg |= 0x0C00; - writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3); - - panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR; - panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR; - - panel_info.epdc_data.wv_modes.mode_init = 0; - panel_info.epdc_data.wv_modes.mode_du = 1; - panel_info.epdc_data.wv_modes.mode_gc4 = 3; - panel_info.epdc_data.wv_modes.mode_gc8 = 2; - panel_info.epdc_data.wv_modes.mode_gc16 = 2; - panel_info.epdc_data.wv_modes.mode_gc32 = 2; - - panel_info.epdc_data.epdc_timings = panel_timings; - - setup_epdc_power(); - - /* Assign fb_base */ - gd->fb_base = CONFIG_FB_BASE; -} - -void epdc_power_on(void) -{ - unsigned int reg; - - /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ - gpio_set_value(IMX_GPIO_NR(2, 20), 1); - udelay(1000); - - /* Enable epdc signal pin */ - epdc_enable_pins(); - - /* Set PMIC Wakeup to high - enable Display power */ - gpio_set_value(IMX_GPIO_NR(3, 20), 1); - - /* Wait for PWRGOOD == 1 */ - while (1) { - reg = readl(GPIO2_BASE_ADDR + GPIO_PSR); - if (!(reg & (1 << 21))) - break; - - udelay(100); - } - - /* Enable VCOM */ - gpio_set_value(IMX_GPIO_NR(3, 17), 1); - - udelay(500); -} - -void epdc_power_off(void) -{ - /* Set PMIC Wakeup to low - disable Display power */ - gpio_set_value(IMX_GPIO_NR(3, 20), 0); - - /* Disable VCOM */ - gpio_set_value(IMX_GPIO_NR(3, 17), 0); - - epdc_disable_pins(); - - /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ - gpio_set_value(IMX_GPIO_NR(2, 20), 0); -} -#endif - int board_init(void) { /* address of boot parameters */ @@ -950,41 +1033,126 @@ int board_init(void) setup_epdc(); #endif +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + return 0; } +static struct pmic *pfuze; int power_init_board(void) { - struct pmic *p; unsigned int reg, ret; - p = pfuze_common_init(I2C_PMIC); - if (!p) + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) return -ENODEV; - ret = pfuze_mode_init(p, APS_PFM); + ret = pfuze_mode_init(pfuze, APS_PFM); if (ret < 0) return ret; /* Increase VGEN3 from 2.5 to 2.8V */ - pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); + pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, ®); reg &= ~LDO_VOL_MASK; reg |= LDOB_2_80V; - pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); + pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg); /* Increase VGEN5 from 2.8 to 3V */ - pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®); reg &= ~LDO_VOL_MASK; reg |= LDOB_3_00V; - pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg); return 0; } -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) { - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; + unsigned int value; + int is_400M; + unsigned char vddarm; + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* increase VDDSOC to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + } + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; +#if defined(CONFIG_MX6DL) + value |= 0x27; +#else + value |= 0x20; +#endif + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* increase VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x28; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + /* + * MX6Q: + * VDDARM:1.15V@800M; VDDSOC:1.175V@800M + * VDDARM:0.975V@400M; VDDSOC:1.175V@400M + * MX6DL: + * VDDARM:1.175V@800M; VDDSOC:1.175V@800M + * VDDARM:1.075V@400M; VDDSOC:1.175V@400M + */ + is_400M = set_anatop_bypass(2); + if (is_400M) +#if defined(CONFIG_MX6DL) + vddarm = 0x1f; +#else + vddarm = 0x1b; +#endif + else +#if defined(CONFIG_MX6DL) + vddarm = 0x23; +#else + vddarm = 0x22; +#endif + + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.175V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x23; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } } #endif @@ -1004,6 +1172,10 @@ int board_late_init(void) #ifdef CONFIG_CMD_BMODE add_board_boot_modes(board_boot_modes); #endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif return 0; } |