diff options
Diffstat (limited to 'board/freescale/mx6q_sabreauto')
| -rw-r--r-- | board/freescale/mx6q_sabreauto/Makefile | 47 | ||||
| -rw-r--r-- | board/freescale/mx6q_sabreauto/config.mk | 7 | ||||
| -rw-r--r-- | board/freescale/mx6q_sabreauto/flash_header.S | 295 | ||||
| -rw-r--r-- | board/freescale/mx6q_sabreauto/lowlevel_init.S | 101 | ||||
| -rw-r--r-- | board/freescale/mx6q_sabreauto/mx6q_sabreauto.c | 437 | ||||
| -rw-r--r-- | board/freescale/mx6q_sabreauto/u-boot.lds | 74 |
6 files changed, 961 insertions, 0 deletions
diff --git a/board/freescale/mx6q_sabreauto/Makefile b/board/freescale/mx6q_sabreauto/Makefile new file mode 100644 index 0000000..60e5fc4 --- /dev/null +++ b/board/freescale/mx6q_sabreauto/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2010-2011 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx6q_sabreauto.o +SOBJS := lowlevel_init.o flash_header.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx6q_sabreauto/config.mk b/board/freescale/mx6q_sabreauto/config.mk new file mode 100644 index 0000000..a0ce2a1 --- /dev/null +++ b/board/freescale/mx6q_sabreauto/config.mk @@ -0,0 +1,7 @@ +LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds + +sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp + +ifndef TEXT_BASE + TEXT_BASE = 0x27800000 +endif diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S new file mode 100644 index 0000000..8790358 --- /dev/null +++ b/board/freescale/mx6q_sabreauto/flash_header.S @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/mx6.h> + +#ifdef CONFIG_FLASH_HEADER +#ifndef CONFIG_FLASH_HEADER_OFFSET +# error "Must define the offset of flash header" +#endif + +.section ".text.flasheader", "x" + b _start + .org CONFIG_FLASH_HEADER_OFFSET + +/* First IVT to copy the plugin that initializes the system into OCRAM */ +ivt_header: .long 0x402000D1 /*Tag=0xD1, Len=0x0020, Ver=0x40 */ +app_code_jump_v: .long 0x00907458 /* Plugin entry point, address after the second IVT table */ +reserv1: .long 0x0 +dcd_ptr: .long 0x0 +boot_data_ptr: .long 0x00907420 +self_ptr: .long 0x00907400 +app_code_csf: .long 0x0 +reserv2: .long 0x0 +boot_data: .long 0x00907000 +image_len: .long 16*1024 /* plugin can be upto 16KB in size */ +plugin: .long 0x1 /* Enable plugin flag */ + +/* Second IVT to give entry point into the bootloader copied to DDR */ +ivt2_header: .long 0x402000D1 /*Tag=0xD1, Len=0x0020, Ver=0x40 */ +app2_code_jump_v: .long _start /* Entry point for uboot */ +reserv3: .long 0x0 +dcd2_ptr: .long 0x0 +boot_data2_ptr: .long boot_data2 +self_ptr2: .long ivt2_header +app_code_csf2: .long 0x0 +reserv4: .long 0x0 +boot_data2: .long TEXT_BASE +image_len2: .long _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET +plugin2: .long 0x0 + +/* Here starts the plugin code */ +plugin_start: +/* Save the return address and the function arguments */ + push {r0-r4, lr} + +/* + * Note: The DDR settings provided below are specific to Freescale development boards and are the latest settings at the time of release. + * However, it is recommended to contact your Freescale representative in case there are any improvements to these settings. + */ + + /* Init the DDR according the init script */ + ldr r0, =CCM_BASE_ADDR + /* select 528MHz for pre_periph_clk_sel */ + ldr r1, =0x00020324 + str r1, [r0,#0x18] + + /* IOMUX setting */ + ldr r0, =IOMUXC_BASE_ADDR + mov r1, #0x30 + str r1, [r0,#0x5a8] + str r1, [r0,#0x5b0] + str r1, [r0,#0x524] + str r1, [r0,#0x51c] + str r1, [r0,#0x518] + str r1, [r0,#0x50c] + str r1, [r0,#0x5b8] + str r1, [r0,#0x5c0] + + ldr r1, =0x00020030 + str r1, [r0,#0x5ac] + str r1, [r0,#0x5b4] + str r1, [r0,#0x528] + str r1, [r0,#0x520] + str r1, [r0,#0x514] + str r1, [r0,#0x510] + str r1, [r0,#0x5bc] + str r1, [r0,#0x5c4] + + str r1, [r0,#0x56c] + str r1, [r0,#0x578] + str r1, [r0,#0x588] + str r1, [r0,#0x594] + str r1, [r0,#0x57c] + + ldr r1, =0x00003000 + str r1, [r0,#0x590] + str r1, [r0,#0x598] + mov r1, #0x00000000 + str r1, [r0,#0x58c] + ldr r1, =0x00003030 + str r1, [r0,#0x59c] + str r1, [r0,#0x5a0] + + ldr r1, =0x00000030 + str r1, [r0,#0x784] + str r1, [r0,#0x788] + str r1, [r0,#0x794] + str r1, [r0,#0x79c] + str r1, [r0,#0x7a0] + str r1, [r0,#0x7a4] + str r1, [r0,#0x7a8] + str r1, [r0,#0x748] + str r1, [r0,#0x74c] + + mov r1, #0x00020000 + str r1, [r0,#0x750] + + mov r1, #0x00000000 + str r1, [r0,#0x758] + + mov r1, #0x00020000 + str r1, [r0,#0x774] + mov r1, #0x30 + str r1, [r0,#0x78c] + mov r1, #0x000c0000 + str r1, [r0,#0x798] + + /* Initialize 2GB DDR3 - Micron MT41J128M */ + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =MMDC_P1_BASE_ADDR + + ldr r1, =0x33333333 + str r1, [r0,#0x81c] + str r1, [r0,#0x820] + str r1, [r0,#0x824] + str r1, [r0,#0x828] + str r1, [r2,#0x81c] + str r1, [r2,#0x820] + str r1, [r2,#0x824] + str r1, [r2,#0x828] + + ldr r1, =0x00081740 + str r1, [r0,#0x18] + ldr r1, =0x00008000 + str r1, [r0,#0x1c] + ldr r1, =0x555a7975 + str r1, [r0,#0x0c] + ldr r1, =0xff538e64 + str r1, [r0,#0x10] + ldr r1, =0x01ff00db + str r1, [r0,#0x14] + + ldr r1, =0x000026d2 + str r1, [r0,#0x2c] + ldr r1, =0x005b0e21 + str r1, [r0,#0x30] + ldr r1, =0x94444040 + str r1, [r0,#0x08] + ldr r1, =0x00020036 + str r1, [r0,#0x04] + ldr r1, =0x00000027 + str r1, [r0,#0x40] + ldr r1, =0xc31a0000 + str r1, [r0,#0x00] + + ldr r1, =0x04088032 + str r1, [r0,#0x1c] + ldr r1, =0x0408803a + str r1, [r0,#0x1c] + ldr r1, =0x00008033 + str r1, [r0,#0x1c] + ldr r1, =0x0000803b + str r1, [r0,#0x1c] + ldr r1, =0x00428031 + str r1, [r0,#0x1c] + ldr r1, =0x00428039 + str r1, [r0,#0x1c] + + ldr r1, =0x09408030 + str r1, [r0,#0x1c] + ldr r1, =0x09408038 + str r1, [r0,#0x1c] + ldr r1, =0x04008040 + str r1, [r0,#0x1c] + ldr r1, =0x04008048 + str r1, [r0,#0x1c] + + ldr r1, =0xa5380003 + str r1, [r0,#0x800] + ldr r1, =0xa5380003 + str r1, [r2,#0x800] + + ldr r1, =0x00005800 + str r1, [r0,#0x20] + + ldr r1, =0x00022227 + str r1, [r0,#0x818] + ldr r1, =0x00022227 + str r1, [r2,#0x818] + + ldr r1, =0x433f033f + str r1, [r0,#0x83c] + + ldr r1, =0x033f033f + str r1, [r0,#0x840] + + ldr r1, =0x433f033f + str r1, [r2,#0x83c] + + ldr r1, =0x0344033b + str r1, [r2,#0x840] + + ldr r1, =0x4337373e + str r1, [r0,#0x848] + ldr r1, =0x3634303d + str r1, [r2,#0x848] + + ldr r1, =0x35374640 + str r1, [r0,#0x850] + ldr r1, =0x4a294b35 + str r1, [r2,#0x850] + + ldr r1, =0x001F001F + str r1, [r0,#0x80c] + ldr r1, =0x001F001F + str r1, [r0,#0x810] + + ldr r1, =0x00440044 + str r1, [r2,#0x80c] + ldr r1, =0x00440044 + str r1, [r2,#0x810] + + ldr r1, =0x00000800 + str r1, [r0,#0x8b8] + ldr r1, =0x00000800 + str r1, [r2,#0x8b8] + + ldr r1, =0x00000000 + str r1, [r0,#0x1c] + +/******************** + The following is to fill in those arguments for this ROM function + pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data) + + This function is used to copy data from the storage media into DDR. + + start - Initial (possibly partial) image load address on entry. Final image load address on exit. + bytes - Initial (possibly partial) image size on entry. Final image size on exit. + boot_data - Initial @ref ivt Boot Data load address. +*/ + + adr r0, DDR_DEST_ADDR + adr r1, COPY_SIZE + adr r2, BOOT_DATA + +/* + * check the _pu_irom_api_table for the address + */ +before_calling_rom___pu_irom_hwcnfg_setup: + mov r4, #0x2000 + add r4, r4, #0xed + blx r4 /* This address might change in future ROM versions */ +after_calling_rom___pu_irom_hwcnfg_setup: + +/* To return to ROM from plugin, we need to fill in these argument. + * Here is what need to do: + * Need to construct the paramters for this function before return to ROM: + * plugin_download(void **start, size_t *bytes, UINT32 *ivt_offset) + */ + pop {r0-r4, lr} + ldr r5, DDR_DEST_ADDR + str r5, [r0] + ldr r5, COPY_SIZE + str r5, [r1] + mov r5, #0x400 /* Point to the second IVT table at offset 0x42C */ + add r5, r5, #0x2C + str r5, [r2] + mov r0, #1 + + bx lr /* return back to ROM code */ + +DDR_DEST_ADDR: .word TEXT_BASE +COPY_SIZE: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET +BOOT_DATA: .word TEXT_BASE + .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET + .word 0 + +#endif diff --git a/board/freescale/mx6q_sabreauto/lowlevel_init.S b/board/freescale/mx6q_sabreauto/lowlevel_init.S new file mode 100644 index 0000000..467af57 --- /dev/null +++ b/board/freescale/mx6q_sabreauto/lowlevel_init.S @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <asm/arch/mx6.h> + +/* + Disable L2Cache because ROM turn it on when uboot use plug-in. + If L2Cache is on default, there are cache coherence problem if kernel have + not config L2Cache. +*/ +.macro init_l2cc + ldr r1, =0xa02000 + ldr r0, =0x0 + str r0, [r1, #0x100] +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips +.endm /* init_aips */ + +.macro setup_pll pll, freq +.endm + +.macro init_clock + +/* PLL1, PLL2, and PLL3 are enabled by ROM */ +#ifdef CONFIG_PLL3 + /* enable PLL3 for UART */ + ldr r0, ANATOP_BASE_ADDR_W + + /* power up PLL */ + ldr r1, [r0, #ANATOP_USB1] + orr r1, r1, #0x1000 + str r1, [r0, #ANATOP_USB1] + + /* enable PLL */ + ldr r1, [r0, #ANATOP_USB1] + orr r1, r1, #0x2000 + str r1, [r0, #ANATOP_USB1] + + /* wait PLL lock */ +100: + ldr r1, [r0, #ANATOP_USB1] + mov r1, r1, lsr #31 + cmp r1, #0x1 + bne 100b + + /* clear bypass bit */ + ldr r1, [r0, #ANATOP_USB1] + and r1, r1, #0xfffeffff + str r1, [r0, #ANATOP_USB1] +#endif + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + ldr r0, CCM_BASE_ADDR_W + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + str r1, [r0, #CLKCTL_CCGR7] + +.endm + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + + init_l2cc + + init_aips + + init_clock + + mov pc, lr + +/* Board level setting value */ +ANATOP_BASE_ADDR_W: .word ANATOP_BASE_ADDR +CCM_BASE_ADDR_W: .word CCM_BASE_ADDR diff --git a/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c b/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c new file mode 100644 index 0000000..068a3f0 --- /dev/null +++ b/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c @@ -0,0 +1,437 @@ +/* + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mx6.h> +#include <asm/arch/mx6_pins.h> +#include <asm/arch/iomux-v3.h> +#include <asm/errno.h> + +#ifdef CONFIG_CMD_MMC +#include <mmc.h> +#include <fsl_esdhc.h> +#endif + +#ifdef CONFIG_ARCH_MMU +#include <asm/mmu.h> +#include <asm/arch/mmu.h> +#endif + +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#include <asm/imx_iim.h> +#endif + +#ifdef CONFIG_CMD_CLOCK +#include <asm/clock.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; +static enum boot_device boot_dev; + +static inline void setup_boot_device(void) +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; + uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; + + switch (bt_mem_ctl) { + case 0x0: + if (bt_mem_type) + boot_dev = ONE_NAND_BOOT; + else + boot_dev = WEIM_NOR_BOOT; + break; + case 0x2: + boot_dev = SATA_BOOT; + break; + case 0x3: + if (bt_mem_type) + boot_dev = SPI_NOR_BOOT; + else + boot_dev = I2C_BOOT; + break; + case 0x4: + case 0x5: + boot_dev = SD_BOOT; + break; + case 0x6: + case 0x7: + boot_dev = MMC_BOOT; + break; + case 0x8 ... 0xf: + boot_dev = NAND_BOOT; + break; + default: + boot_dev = UNKNOWN_BOOT; + break; + } +} + +enum boot_device get_boot_device(void) +{ + return boot_dev; +} + +u32 get_board_rev(void) +{ + + system_rev = 0x63000; + + return system_rev; +} + +#ifdef CONFIG_ARCH_MMU +void board_mmu_init(void) +{ + unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000; + unsigned long i; + + /* + * Set the TTB register + */ + asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + + /* + * Set the Domain Access Control Register + */ + i = ARM_ACCESS_DACR_DEFAULT; + asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + + /* + * First clear all TT entries - ie Set them to Faulting + */ + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + /* Actual Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0x000, 0x001, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* ROM, 1M */ + X_ARM_MMU_SECTION(0x001, 0x001, 0x008, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* 8M */ + X_ARM_MMU_SECTION(0x009, 0x009, 0x001, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* IRAM */ + X_ARM_MMU_SECTION(0x00A, 0x00A, 0x0F6, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* 246M */ + /* 2 GB memory starting at 0x10000000, only map 1.875 GB */ + X_ARM_MMU_SECTION(0x100, 0x100, 0x780, + ARM_CACHEABLE, ARM_BUFFERABLE, + ARM_ACCESS_PERM_RW_RW); + /* uncached alias of the same 1.875 GB memory */ + X_ARM_MMU_SECTION(0x100, 0x880, 0x780, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); + + /* Enable MMU */ + MMU_ON(); +} +#endif + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + return 0; +} + +static void setup_uart(void) +{ + /* UART4 TXD */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL0__UART4_TXD); + + /* UART4 RXD */ + mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW0__UART4_RXD); +} + +#define HW_OCOTP_MACn(n) (0x00000620 + (n) * 0x10) + +#ifdef CONFIG_MXC_FEC +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM + +int fec_get_mac_addr(unsigned char *mac) +{ + u32 *ocotp_mac_base = + (u32 *)(OCOTP_BASE_ADDR + HW_OCOTP_MACn(0)); + int i; + + for (i = 0; i < 6; ++i, ++ocotp_mac_base) + mac[6 - 1 - i] = readl(++ocotp_mac_base); + return 0; +} + +#endif +#endif + + +#ifdef CONFIG_NET_MULTI +int board_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + + return rc; +} +#endif + +#ifdef CONFIG_CMD_MMC + +struct fsl_esdhc_cfg usdhc_cfg[4] = { + {USDHC1_BASE_ADDR, 1, 1}, + {USDHC2_BASE_ADDR, 1, 1}, + {USDHC3_BASE_ADDR, 1, 1}, + {USDHC4_BASE_ADDR, 1, 1}, +}; + +#ifdef CONFIG_DYNAMIC_MMC_DEVNO +int get_mmc_env_devno(void) +{ + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + + /* BOOT_CFG2[3] and BOOT_CFG2[4] */ + return (soc_sbmr & 0x00001800) >> 11; +} +#endif + +iomux_v3_cfg_t mx6q_usdhc1_pads[] = { + MX6Q_PAD_SD1_CLK__USDHC1_CLK, + MX6Q_PAD_SD1_CMD__USDHC1_CMD, + MX6Q_PAD_SD1_DAT0__USDHC1_DAT0, + MX6Q_PAD_SD1_DAT1__USDHC1_DAT1, + MX6Q_PAD_SD1_DAT2__USDHC1_DAT2, + MX6Q_PAD_SD1_DAT3__USDHC1_DAT3, +}; +iomux_v3_cfg_t mx6q_usdhc2_pads[] = { + MX6Q_PAD_SD2_CLK__USDHC2_CLK, + MX6Q_PAD_SD2_CMD__USDHC2_CMD, + MX6Q_PAD_SD2_DAT0__USDHC2_DAT0, + MX6Q_PAD_SD2_DAT1__USDHC2_DAT1, + MX6Q_PAD_SD2_DAT2__USDHC2_DAT2, + MX6Q_PAD_SD2_DAT3__USDHC2_DAT3, +}; +iomux_v3_cfg_t mx6q_usdhc3_pads[] = { + MX6Q_PAD_SD3_CLK__USDHC3_CLK, + MX6Q_PAD_SD3_CMD__USDHC3_CMD, + MX6Q_PAD_SD3_DAT0__USDHC3_DAT0, + MX6Q_PAD_SD3_DAT1__USDHC3_DAT1, + MX6Q_PAD_SD3_DAT2__USDHC3_DAT2, + MX6Q_PAD_SD3_DAT3__USDHC3_DAT3, + MX6Q_PAD_SD3_DAT4__USDHC3_DAT4, + MX6Q_PAD_SD3_DAT5__USDHC3_DAT5, + MX6Q_PAD_SD3_DAT6__USDHC3_DAT6, + MX6Q_PAD_SD3_DAT7__USDHC3_DAT7, +}; +iomux_v3_cfg_t mx6q_usdhc4_pads[] = { + MX6Q_PAD_SD4_CLK__USDHC4_CLK, + MX6Q_PAD_SD4_CMD__USDHC4_CMD, + MX6Q_PAD_SD4_DAT0__USDHC4_DAT0, + MX6Q_PAD_SD4_DAT1__USDHC4_DAT1, + MX6Q_PAD_SD4_DAT2__USDHC4_DAT2, + MX6Q_PAD_SD4_DAT3__USDHC4_DAT3, + MX6Q_PAD_SD4_DAT4__USDHC4_DAT4, + MX6Q_PAD_SD4_DAT5__USDHC4_DAT5, + MX6Q_PAD_SD4_DAT6__USDHC4_DAT6, + MX6Q_PAD_SD4_DAT7__USDHC4_DAT7, +}; + +int usdhc_gpio_init(bd_t *bis) +{ + s32 status = 0; + u32 index = 0; + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; + ++index) { + switch (index) { + case 0: + mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc1_pads, + sizeof(mx6q_usdhc1_pads) / sizeof(mx6q_usdhc1_pads[0])); + break; + case 1: + mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc2_pads, + sizeof(mx6q_usdhc2_pads) / sizeof(mx6q_usdhc2_pads[0])); + break; + case 2: + mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc3_pads, + sizeof(mx6q_usdhc3_pads) / sizeof(mx6q_usdhc3_pads[0])); + break; + case 3: + mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc4_pads, + sizeof(mx6q_usdhc4_pads) / sizeof(mx6q_usdhc4_pads[0])); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + index+1, CONFIG_SYS_FSL_USDHC_NUM); + return status; + } + status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + } + + return status; +} + +int board_mmc_init(bd_t *bis) +{ + if (!usdhc_gpio_init(bis)) + return 0; + else + return -1; +} + +#endif + +int board_init(void) +{ +#ifdef CONFIG_MFG +/* MFG firmware need reset usb to avoid host crash firstly */ +#define USBCMD 0x140 + int val = readl(OTG_BASE_ADDR + USBCMD); + val &= ~0x1; /*RS bit*/ + writel(val, OTG_BASE_ADDR + USBCMD); +#endif + mxc_iomux_v3_init((void *)IOMUXC_BASE_ADDR); + setup_boot_device(); + + /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_MX6Q_SABREAUTO; + + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + setup_uart(); + + return 0; +} + +int board_late_init(void) +{ + printf("board_late_init\n"); + return 0; +} + +iomux_v3_cfg_t enet_pads[] = { + MX6Q_PAD_KEY_COL1__ENET_MDIO, + MX6Q_PAD_KEY_COL2__ENET_MDC, + MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC, + MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0, + MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1, + MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2, + MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3, + MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL, + MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC, + MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0, + MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1, + MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2, + MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3, + MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL, +}; + +void enet_board_init(void) +{ + unsigned int reg; + iomux_v3_cfg_t enet_reset = + (MX6Q_PAD_KEY_ROW4__GPIO_4_15 & + ~MUX_PAD_CTRL_MASK) | + MUX_PAD_CTRL(0x84); + + mxc_iomux_v3_setup_multiple_pads(enet_pads, + ARRAY_SIZE(enet_pads)); + + mxc_iomux_v3_setup_pad(enet_reset); + + printf("enet_board_init\n"); + /* phy reset: gpio4-15 */ + reg = readl(GPIO4_BASE_ADDR + 0x0); + reg &= ~0x8000; + writel(reg, GPIO4_BASE_ADDR + 0x0); + + reg = readl(GPIO4_BASE_ADDR + 0x4); + reg |= 0x8000; + writel(reg, GPIO4_BASE_ADDR + 0x4); + + udelay(500); + + reg = readl(GPIO4_BASE_ADDR + 0x0); + reg |= 0x8000; + writel(reg, GPIO4_BASE_ADDR + 0x0); +} + +int checkboard(void) +{ + printf("Board: MX6Q-SABREAUTO:[ "); + + switch (__REG(SRC_BASE_ADDR + 0x8)) { + case 0x0001: + printf("POR"); + break; + case 0x0009: + printf("RST"); + break; + case 0x0010: + case 0x0011: + printf("WDOG"); + break; + default: + printf("unknown"); + } + printf("]\n"); + + printf("Boot Device: "); + switch (get_boot_device()) { + case WEIM_NOR_BOOT: + printf("NOR\n"); + break; + case ONE_NAND_BOOT: + printf("ONE NAND\n"); + break; + case PATA_BOOT: + printf("PATA\n"); + break; + case SATA_BOOT: + printf("SATA\n"); + break; + case I2C_BOOT: + printf("I2C\n"); + break; + case SPI_NOR_BOOT: + printf("SPI NOR\n"); + break; + case SD_BOOT: + printf("SD\n"); + break; + case MMC_BOOT: + printf("MMC\n"); + break; + case NAND_BOOT: + printf("NAND\n"); + break; + case UNKNOWN_BOOT: + default: + printf("UNKNOWN\n"); + break; + } + return 0; +} diff --git a/board/freescale/mx6q_sabreauto/u-boot.lds b/board/freescale/mx6q_sabreauto/u-boot.lds new file mode 100644 index 0000000..f3ebb48 --- /dev/null +++ b/board/freescale/mx6q_sabreauto/u-boot.lds @@ -0,0 +1,74 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * (C) Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + board/freescale/mx6q_sabreauto/flash_header.o (.text.flasheader) + cpu/arm_cortexa8/start.o + board/freescale/mx6q_sabreauto/libmx6q_sabreauto.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + drivers/mmc/libmmc.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _end_of_copy = .; /* end_of ROM copy code here */ + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} |