diff options
Diffstat (limited to 'board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg')
| -rw-r--r-- | board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg | 600 |
1 files changed, 600 insertions, 0 deletions
diff --git a/board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg b/board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg new file mode 100644 index 0000000..d95b9bc --- /dev/null +++ b/board/freescale/mx6dqscm/imximage_scm_lpddr2.cfg @@ -0,0 +1,600 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6dscm/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#ifdef CONFIG_SCM_LPDDR2_512MB +/* DCD */ +/* DDR clock to 400MHz */ +DATA 4, 0x020C4018 0x00060324 +/* AHB_ROOT_CLK change divide ratio from 4 to 3 for ENET */ +DATA 4, 0x020C4014 0x00018900 + +DATA 4 0x020C4018 0x00060324 + +DATA 4 0x020e0798 0x00080000 +DATA 4 0x020e0758 0x00000000 + +DATA 4 0x020E0588 0x00000030 +DATA 4 0x020E0594 0x00000030 + +DATA 4 0x020E056c 0x00000030 +DATA 4 0x020E0578 0x00000030 +DATA 4 0x020E074c 0x00000030 + +DATA 4 0x020E057c 0x00000030 +DATA 4 0x020E058c 0x00000000 +DATA 4 0x020E059c 0x00000030 +DATA 4 0x020E05a0 0x00000030 +DATA 4 0x020E078c 0x00000030 + +DATA 4 0x020E0750 0x00020000 +DATA 4 0x020E05a8 0x00003030 +DATA 4 0x020E05b0 0x00003030 +DATA 4 0x020E0524 0x00003030 +DATA 4 0x020E051c 0x00003030 +DATA 4 0x020E0518 0x00003030 +DATA 4 0x020E050c 0x00003030 +DATA 4 0x020E05b8 0x00003030 +DATA 4 0x020E05c0 0x00003030 + +DATA 4 0x020E0774 0x00020000 + +DATA 4 0x020E0784 0x00000030 +DATA 4 0x020E0788 0x00000030 +DATA 4 0x020E0794 0x00000030 +DATA 4 0x020E079c 0x00000030 +DATA 4 0x020E07a0 0x00000030 +DATA 4 0x020E07a4 0x00000030 +DATA 4 0x020E07a8 0x00000030 +DATA 4 0x020E0748 0x00000030 + +DATA 4 0x020E05ac 0x00000030 +DATA 4 0x020E05b4 0x00000030 +DATA 4 0x020E0528 0x00000030 +DATA 4 0x020E0520 0x00000030 +DATA 4 0x020E0514 0x00000030 +DATA 4 0x020E0510 0x00000030 +DATA 4 0x020E05bc 0x00000030 +DATA 4 0x020E05c4 0x00000030 + +DATA 4 0x020E0590 0x00000020 +DATA 4 0x020E0598 0x00000020 + +DATA 4 0x021b001c 0x00008000 + +DATA 4 0x021b085c 0x1b4700c7 + +DATA 4 0x021b0800 0xa1390003 + + +DATA 4 0x021b0890 0x00400000 + +DATA 4 0x021b0848 0x44404044 + +DATA 4 0x021b0850 0x34343A38 + +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 + +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b000c 0x33374133 + +DATA 4 0x021b0010 0x00100a82 + +DATA 4 0x021b0014 0x00000093 + +DATA 4 0x021b0018 0x0000174C +DATA 4 0x021b001c 0x00008050 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x00000010 +DATA 4 0x021b0038 0x00190778 + +/* 1-Ch Mode */ +DATA 4 0x021b0040 0x0000004f + +DATA 4 0x021b0000 0x83110000 + +/* Channel 0 */ +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x04038030 + +DATA 4 0x021b0800 0xa1390003 + +DATA 4 0x021b0020 0x00001800 + +DATA 4 0x021b0818 0x00000000 + +DATA 4 0x021b0004 0x00025576 + +DATA 4 0x021b0404 0x00011006 + +DATA 4 0x021b001c 0x00000000 + + +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +#elif CONFIG_SCM_LPDDR2_2GB +/* DDR clock to 400MHz */ +DATA 4, 0x020C4018 0x00060324 +/* AHB_ROOT_CLK change divide ratio from 4 to 3 for ENET */ +DATA 4, 0x020C4014 0x00018900 + +DATA 4, 0x020e0798, 0x00080000 +DATA 4, 0x020e0758, 0x00000000 + + + +DATA 4, 0x020E0588, 0x00000030 +DATA 4, 0x020E0594, 0x00000030 + +DATA 4, 0x020E056c, 0x00000030 +DATA 4, 0x020E0578, 0x00000030 +DATA 4, 0x020E074c, 0x00000030 + +DATA 4, 0x020E057c, 0x00000030 +DATA 4, 0x020E058c, 0x00000000 +DATA 4, 0x020E059c, 0x00000030 +DATA 4, 0x020E05a0, 0x00000030 +DATA 4, 0x020E078c, 0x00000030 + +DATA 4, 0x020E0750, 0x00020000 +DATA 4, 0x020E05a8, 0x00003030 +DATA 4, 0x020E05b0, 0x00003030 +DATA 4, 0x020E0524, 0x00003030 +DATA 4, 0x020E051c, 0x00003030 +DATA 4, 0x020E0518, 0x00003030 +DATA 4, 0x020E050c, 0x00003030 +DATA 4, 0x020E05b8, 0x00003030 +DATA 4, 0x020E05c0, 0x00003030 + +DATA 4, 0x020E0774, 0x00020000 + +DATA 4, 0x020E0784, 0x00000030 +DATA 4, 0x020E0788, 0x00000030 +DATA 4, 0x020E0794, 0x00000030 +DATA 4, 0x020E079c, 0x00000030 +DATA 4, 0x020E07a0, 0x00000030 +DATA 4, 0x020E07a4, 0x00000030 +DATA 4, 0x020E07a8, 0x00000030 +DATA 4, 0x020E0748, 0x00000030 + +DATA 4, 0x020E05ac, 0x00000030 +DATA 4, 0x020E05b4, 0x00000030 +DATA 4, 0x020E0528, 0x00000030 +DATA 4, 0x020E0520, 0x00000030 +DATA 4, 0x020E0514, 0x00000030 +DATA 4, 0x020E0510, 0x00000030 +DATA 4, 0x020E05bc, 0x00000030 +DATA 4, 0x020E05c4, 0x00000030 + + + +DATA 4, 0x020E0590, 0x00000020 +DATA 4, 0x020E0598, 0x00000020 + +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b401c, 0x00008000 + +DATA 4, 0x021b085c, 0x1b4700c7 +DATA 4, 0x021b485c, 0x1b4700c7 + +DATA 4, 0x021b0800, 0xa1390003 + +DATA 4, 0x021b0890, 0x00400000 +DATA 4, 0x021b4890, 0x00400000 + +DATA 4, 0x021b0848, 0x44404044 +DATA 4, 0x021b4848, 0x44443A46 + +DATA 4, 0x021b0850, 0x34343A38 +DATA 4, 0x021b4850, 0x382F3835 + +DATA 4, 0x021b083c, 0x20000000 +DATA 4, 0x021b0840, 0x00000000 +DATA 4, 0x021b483c, 0x20000000 +DATA 4, 0x021b4840, 0x00000000 + +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b481c, 0x33333333 +DATA 4, 0x021b4820, 0x33333333 +DATA 4, 0x021b4824, 0x00000000 +DATA 4, 0x021b4828, 0x33333333 +DATA 4, 0x021b082c, 0xf3333333 +DATA 4, 0x021b0830, 0xf3333333 +DATA 4, 0x021b0834, 0xf3333333 +DATA 4, 0x021b0838, 0xf3333333 +DATA 4, 0x021b482c, 0xf3333333 +DATA 4, 0x021b4830, 0xf3333333 +DATA 4, 0x021b4834, 0x00000000 +DATA 4, 0x021b4838, 0xf3333333 + +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b48b8, 0x00000800 + +DATA 4, 0x021b0004, 0x00020036 +DATA 4, 0x021b0008, 0x00000000 +DATA 4, 0x021b000c, 0x33374133 + +DATA 4, 0x021b0010, 0x00100a82 + +DATA 4, 0x021b0014, 0x00000093 + +DATA 4, 0x021b0018, 0x0000174C +DATA 4, 0x021b001c, 0x00008050 +DATA 4, 0x021b002c, 0x0f9f26d2 +DATA 4, 0x021b0030, 0x009F0E10 +DATA 4, 0x021b0038, 0x00190778 + +#ifdef CONFIG_INTERLEAVING_MODE +DATA 4, 0x021b0040, 0x00000053 +#else +DATA 4, 0x021b0040, 0x0000004f +#endif + +DATA 4, 0x021b0000, 0xc3110000 + +DATA 4, 0x021b4004, 0x00020036 +DATA 4, 0x021b4008, 0x00000000 + +DATA 4, 0x021b400c, 0x33374133 + +DATA 4, 0x021b4010, 0x00100a82 + +DATA 4, 0x021b4014, 0x00000093 + +DATA 4, 0x021b4018, 0x0000174C +DATA 4, 0x021b401c, 0x00008050 + +DATA 4, 0x021b402c, 0x0f9f26d2 + +DATA 4, 0x021b4030, 0x009F0E10 + +DATA 4, 0x021b4038, 0x00190778 + +#ifdef CONFIG_INTERLEAVING_MODE +DATA 4, 0x021b4040, 0x00000013 +#else +DATA 4, 0x021b4040, 0x00000017 +#endif + +DATA 4, 0x021b4000, 0xc3110000 + +/* Channel 0 */ +/* CS0 */ +DATA 4, 0x021b001c, 0x003f8030 +DATA 4, 0x021b001c, 0xff0a8030 +DATA 4, 0x021b001c, 0x82018030 +DATA 4, 0x021b001c, 0x04028030 +DATA 4, 0x021b001c, 0x04038030 +DATA 4, 0x021b001c, 0x01038030 +/* CS1 */ +DATA 4, 0x021b001c, 0x003f8038 +DATA 4, 0x021b001c, 0xff0a8038 +DATA 4, 0x021b001c, 0x82018038 +DATA 4, 0x021b001c, 0x04028038 +DATA 4, 0x021b001c, 0x04038038 +DATA 4, 0x021b001c, 0x01038038 + +/* Channel 1 */ +/* CS0 */ +DATA 4, 0x021b401c, 0x003f8030 +DATA 4, 0x021b401c, 0xff0a8030 +DATA 4, 0x021b401c, 0x82018030 +DATA 4, 0x021b401c, 0x04028030 +DATA 4, 0x021b401c, 0x04038030 +DATA 4, 0x021b401c, 0x01038030 +/* CS1 */ +DATA 4, 0x021b401c, 0x003f8038 +DATA 4, 0x021b401c, 0xff0a8038 +DATA 4, 0x021b401c, 0x82018038 +DATA 4, 0x021b401c, 0x04028038 +DATA 4, 0x021b401c, 0x04038038 +DATA 4, 0x021b401c, 0x01038038 +DATA 4, 0x021b4800, 0xa1390003 + +DATA 4, 0x021b0020, 0x00001800 +DATA 4, 0x021b4020, 0x00001800 + +DATA 4, 0x021b0818, 0x00000000 +DATA 4, 0x021b4818, 0x00000000 + +DATA 4, 0x021b0004, 0x00025576 +DATA 4, 0x021b4004, 0x00025576 + +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b4404, 0x00011006 + +DATA 4, 0x021b001c, 0x00000000 +DATA 4, 0x021b401c, 0x00000000 + +/* enable clocks */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F + +#else +/* DCD */ +/* DDR clock to 400MHz */ +DATA 4, 0x020C4018 0x00060324 +/* AHB_ROOT_CLK change divide ratio from 4 to 3 for ENET */ +DATA 4, 0x020C4014 0x00018900 + +/* DSE to 80 ohms, 100K PD on DQS */ +DATA 4 0x020e0798 0x00080000 +DATA 4 0x020e0758 0x00000000 + + + +DATA 4, 0x020E0588, 0x00000030 +DATA 4, 0x020E0594, 0x00000030 + +DATA 4, 0x020E056c, 0x00000030 +DATA 4, 0x020E0578, 0x00000030 +DATA 4, 0x020E074c, 0x00000030 + +DATA 4, 0x020E057c, 0x00000030 +DATA 4, 0x020E058c, 0x00000000 +DATA 4, 0x020E059c, 0x00000030 +DATA 4, 0x020E05a0, 0x00000030 +DATA 4, 0x020E078c, 0x00000030 + +DATA 4, 0x020E0750, 0x00020000 +DATA 4, 0x020E05a8, 0x00003030 +DATA 4, 0x020E05b0, 0x00003030 +DATA 4, 0x020E0524, 0x00003030 +DATA 4, 0x020E051c, 0x00003030 +DATA 4, 0x020E0518, 0x00003030 +DATA 4, 0x020E050c, 0x00003030 +DATA 4, 0x020E05b8, 0x00003030 +DATA 4, 0x020E05c0, 0x00003030 + +DATA 4, 0x020E0774, 0x00020000 + +DATA 4, 0x020E0784, 0x00000030 +DATA 4, 0x020E0788, 0x00000030 +DATA 4, 0x020E0794, 0x00000030 +DATA 4, 0x020E079c, 0x00000030 +DATA 4, 0x020E07a0, 0x00000030 +DATA 4, 0x020E07a4, 0x00000030 +DATA 4, 0x020E07a8, 0x00000030 +DATA 4, 0x020E0748, 0x00000030 + +DATA 4, 0x020E05ac, 0x00000030 +DATA 4, 0x020E05b4, 0x00000030 +DATA 4, 0x020E0528, 0x00000030 +DATA 4, 0x020E0520, 0x00000030 +DATA 4, 0x020E0514, 0x00000030 +DATA 4, 0x020E0510, 0x00000030 +DATA 4, 0x020E05bc, 0x00000030 +DATA 4, 0x020E05c4, 0x00000030 + + + +DATA 4, 0x020E0590, 0x00000020 +DATA 4, 0x020E0598, 0x00000020 + + +/* DDR setup */ +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b401c, 0x00008000 + +/*SCM CONF*/ + +DATA 4, 0x021b085c, 0x1b4700c7 +DATA 4, 0x021b485c, 0x1b4700c7 + +DATA 4, 0x021b0800, 0xa1390003 + +/* calibration required */ +DATA 4, 0x021b0890, 0x00400000 +DATA 4, 0x021b4890, 0x00400000 + +/* calibration required */ +/*SCM CONF*/ + +DATA 4, 0x021b0848, 0x44404044 +DATA 4, 0x021b4848, 0x44443A46 + +DATA 4, 0x021b0850, 0x34343A38 +DATA 4, 0x021b4850, 0x3E2E483C + +DATA 4, 0x021b083c, 0x20000000 +DATA 4, 0x021b0840, 0x00000000 +DATA 4, 0x021b483c, 0x20000000 +DATA 4, 0x021b4840, 0x00000000 + +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b481c, 0x33333333 +DATA 4, 0x021b4820, 0x33333333 +DATA 4, 0x021b4824, 0x33333333 +DATA 4, 0x021b4828, 0x33333333 +DATA 4, 0x021b082c, 0xf3333333 +DATA 4, 0x021b0830, 0xf3333333 +DATA 4, 0x021b0834, 0xf3333333 +DATA 4, 0x021b0838, 0xf3333333 +DATA 4, 0x021b482c, 0xf3333333 +DATA 4, 0x021b4830, 0xf3333333 +DATA 4, 0x021b4834, 0xf3333333 +DATA 4, 0x021b4838, 0xf3333333 + +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b48b8, 0x00000800 + +DATA 4, 0x021b0004, 0x00020036 +DATA 4, 0x021b0008, 0x00000000 +DATA 4, 0x021b000c, 0x33374133 + +DATA 4, 0x021b0010, 0x00100a82 + +DATA 4, 0x021b0014, 0x00000093 + +DATA 4, 0x021b0018, 0x0000174C +DATA 4, 0x021b001c, 0x00008050 +DATA 4, 0x021b002c, 0x0f9f26d2 +DATA 4, 0x021b0030, 0x00000010 +DATA 4, 0x021b0038, 0x00190778 +#ifdef CONFIG_INTERLEAVING_MODE +DATA 4, 0x021b0040, 0x00000053 +#else +DATA 4, 0x021b0040, 0x0000004f +#endif + +DATA 4, 0x021b0000, 0x83110000 + +DATA 4, 0x021b4008, 0x00000000 + +DATA 4, 0x021b400c, 0x33374133 +DATA 4, 0x021b4004, 0x00020036 +DATA 4, 0x021b4010, 0x00100a82 + +DATA 4, 0x021b4014, 0x00000093 + +DATA 4, 0x021b4018, 0x0000174C +DATA 4, 0x021b401c, 0x00008050 + +DATA 4, 0x021b402c, 0x0f9f26d2 + +DATA 4, 0x021b4030, 0x00000010 + +DATA 4, 0x021b4038, 0x00190778 +#ifdef CONFIG_INTERLEAVING_MODE +DATA 4, 0x021b4040, 0x00000013 +#else +DATA 4, 0x021b4040, 0x00000017 +#endif + +DATA 4, 0x021b4000, 0x83110000 + +/* Channel 0 */ +DATA 4, 0x021b001c, 0x003f8030 +DATA 4, 0x021b001c, 0xff0a8030 +DATA 4, 0x021b001c, 0x82018030 +DATA 4, 0x021b001c, 0x04028030 +DATA 4, 0x021b001c, 0x04038030 + +/* Channel 1 */ +DATA 4, 0x021b401c, 0x003f8030 +DATA 4, 0x021b401c, 0xff0a8030 +DATA 4, 0x021b401c, 0x82018030 +DATA 4, 0x021b401c, 0x04028030 +DATA 4, 0x021b401c, 0x04038030 + +DATA 4, 0x021b0800, 0xa1390003 + +DATA 4, 0x021b0020, 0x00001800 +DATA 4, 0x021b4020, 0x00001800 + +DATA 4, 0x021b0818, 0x00000000 +DATA 4, 0x021b4818, 0x00000000 + +DATA 4, 0x021b0004, 0x00025576 +DATA 4, 0x021b4004, 0x00025576 + +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b4404, 0x00011006 + +DATA 4, 0x021b001c, 0x00000000 +DATA 4, 0x021b401c, 0x00000000 + +/* enable clocks */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif /*CONFIG_SCM_LPDDR2_2GB*/ +#endif |