diff options
Diffstat (limited to 'board/freescale/mpc8569mds/bcsr.c')
| -rw-r--r-- | board/freescale/mpc8569mds/bcsr.c | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c index f462597..a936edb 100644 --- a/board/freescale/mpc8569mds/bcsr.c +++ b/board/freescale/mpc8569mds/bcsr.c @@ -35,12 +35,29 @@ void disable_8569mds_flash_write() clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP); } -void enable_8569mds_qe_mdio() +void enable_8569mds_qe_uec() { +#if defined(CONFIG_SYS_UCC_RGMII_MODE) setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), + BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), + BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); +#elif defined(CONFIG_SYS_UCC_RMII_MODE) + /* Set UCC1-4 working at RMII mode */ + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), + BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN); + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8), + BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN); + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), + BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN); + clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10), + BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN); + setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN); +#endif } void disable_8569mds_brd_eeprom_write_protect() |