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Diffstat (limited to 'board/freescale/mpc8548cds/mpc8548cds.c')
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c25
1 files changed, 1 insertions, 24 deletions
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index af5ff42..c562fc9 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -38,10 +38,6 @@
#include "../common/eeprom.h"
#include "../common/via.h"
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void);
@@ -56,7 +52,6 @@ int checkboard (void)
uint pci_slot = get_pci_slot ();
uint cpu_board_rev = get_cpu_board_revision ();
- uint svr;
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot);
@@ -69,17 +64,6 @@ int checkboard (void)
*/
local_bus_init ();
- svr = get_svr();
-
- /*
- * Fix CPU2 errata: A core hang possible while executing a
- * msync instruction and a snoopable transaction from an I/O
- * master tagged to make quick forward progress is present.
- * Fixed in Silicon Rev.2.1
- */
- if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
- ecm->eebpcr |= (1 << 16);
-
/*
* Hack TSEC 3 and 4 IO voltages.
*/
@@ -118,13 +102,6 @@ initdram(int board_type)
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
-
/*
* SDRAM Initialization
*/
@@ -355,7 +332,7 @@ pci_init_board(void)
first_free_busno=hose->last_busno+1;
printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
#ifdef CONFIG_PCIX_CHECK
- if (!(gur->pordevsr & PORDEVSR_PCI)) {
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
/* PCI-X init */
if (CONFIG_SYS_CLK_FREQ < 66000000)
printf("PCI-X will only work at 66 MHz\n");