diff options
Diffstat (limited to 'board/freescale/mpc8536ds/tlb.c')
| -rw-r--r-- | board/freescale/mpc8536ds/tlb.c | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index 28a9fa8..c81a959 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -28,16 +28,16 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), @@ -47,25 +47,30 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 1, BOOKE_PAGESZ_256M, 1), /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1G, 1), /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256K, 1), + + /* *I*G - NAND */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_1M, 1), }; int num_tlb_entries = ARRAY_SIZE(tlb_table); |