diff options
Diffstat (limited to 'board/freescale/mpc837xerdb/mpc837xerdb.c')
| -rw-r--r-- | board/freescale/mpc837xerdb/mpc837xerdb.c | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c index aaefc18..318a3dc 100644 --- a/board/freescale/mpc837xerdb/mpc837xerdb.c +++ b/board/freescale/mpc837xerdb/mpc837xerdb.c @@ -20,17 +20,17 @@ #include <spd_sdram.h> #include <vsc7385.h> -#if defined(CFG_DRAM_TEST) +#if defined(CONFIG_SYS_DRAM_TEST) int testdram(void) { - uint *pstart = (uint *) CFG_MEMTEST_START; - uint *pend = (uint *) CFG_MEMTEST_END; + uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; + uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; uint *p; printf("Testing DRAM from 0x%08x to 0x%08x\n", - CFG_MEMTEST_START, - CFG_MEMTEST_END); + CONFIG_SYS_MEMTEST_START, + CONFIG_SYS_MEMTEST_END); printf("DRAM test phase 1:\n"); for (p = pstart; p < pend; p++) @@ -66,7 +66,7 @@ int fixed_sdram(void); phys_size_t initdram(int board_type) { - immap_t *im = (immap_t *) CFG_IMMR; + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) @@ -92,40 +92,40 @@ phys_size_t initdram(int board_type) ************************************************************************/ int fixed_sdram(void) { - immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = CFG_DDR_SIZE * 1024 * 1024; + immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; udelay(50000); - im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; udelay(1000); - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; udelay(1000); - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; sync(); udelay(1000); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; udelay(2000); - return CFG_DDR_SIZE; + return CONFIG_SYS_DDR_SIZE; } -#endif /*!CFG_SPD_EEPROM */ +#endif /*!CONFIG_SYS_SPD_EEPROM */ int checkboard(void) { @@ -136,7 +136,7 @@ int checkboard(void) int board_early_init_f(void) { #ifdef CONFIG_FSL_SERDES - immap_t *immr = (immap_t *)CFG_IMMR; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; u32 spridr = in_be32(&immr->sysconf.spridr); /* we check only part num, and don't look for CPU revisions */ @@ -148,7 +148,7 @@ int board_early_init_f(void) FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: - fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8379: |