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-rw-r--r--board/freescale/mpc8360emds/mpc8360emds.c61
-rw-r--r--board/freescale/mpc8360emds/pci.c46
2 files changed, 65 insertions, 42 deletions
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index e050cd4..2fcef8b 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -25,9 +25,7 @@
#else
#include <asm/mmu.h>
#endif
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif
#if defined(CONFIG_PQ_MDS_PIB)
@@ -87,6 +85,11 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
+ {5, 0, 1, 0, 2}, /* UART2_SOUT */
+ {5, 1, 2, 0, 3}, /* UART2_CTS */
+ {5, 2, 1, 0, 1}, /* UART2_RTS */
+ {5, 3, 2, 0, 2}, /* UART2_SIN */
+
{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};
@@ -106,6 +109,9 @@ int board_early_init_f(void)
immr->sysconf.spridr == SPR_8360E_REV21)
bcsr[0xe] = 0x30;
+ /* Enable second UART */
+ bcsr[0x9] &= ~0x01;
+
return 0;
}
@@ -295,19 +301,48 @@ void sdram_init(void)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
-#if defined(CONFIG_OF_FLAT_TREE)
- u32 *p;
- int len;
-
- p = ft_get_prop(blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32(bd->bi_memstart);
- *p = cpu_to_be32(bd->bi_memsize);
- }
-#endif
+ const immap_t *immr = (immap_t *)CFG_IMMR;
+
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
+ /*
+ * mpc8360ea pb mds errata 2: RGMII timing
+ * if on mpc8360ea rev. 2.1,
+ * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
+ */
+ if (immr->sysconf.spridr == SPR_8360_REV21 ||
+ immr->sysconf.spridr == SPR_8360E_REV21) {
+ int nodeoffset;
+ const char *prop;
+ const char *path;
+
+ nodeoffset = fdt_path_offset(fdt, "/aliases");
+ if (nodeoffset >= 0) {
+#if defined(CONFIG_HAS_ETH0)
+ /* fixup UCC 1 if using rgmii-id mode */
+ path = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
+ if (path) {
+ prop = fdt_getprop(blob, nodeoffset,
+ "phy-connection-type", 0);
+ if (prop && (strcmp(prop, "rgmii-id") == 0))
+ fdt_setprop(blob, nodeoffset, "phy-connection-type",
+ "rgmii-rxid", sizeof("rgmii-rxid"));
+ }
+#endif
+#if defined(CONFIG_HAS_ETH1)
+ /* fixup UCC 2 if using rgmii-id mode */
+ path = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
+ if (path) {
+ prop = fdt_getprop(blob, nodeoffset,
+ "phy-connection-type", 0);
+ if (prop && (strcmp(prop, "rgmii-id") == 0))
+ fdt_setprop(blob, nodeoffset, "phy-connection-type",
+ "rgmii-rxid", sizeof("rgmii-rxid"));
+ }
+#endif
+ }
+ }
}
#endif
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
index f18e532..4a0d460 100644
--- a/board/freescale/mpc8360emds/pci.c
+++ b/board/freescale/mpc8360emds/pci.c
@@ -18,10 +18,9 @@
#include <common.h>
#include <pci.h>
#include <i2c.h>
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-#elif defined(CONFIG_OF_LIBFDT)
+#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
+#include <fdt_support.h>
#endif
#include <asm/fsl_i2c.h>
@@ -262,37 +261,26 @@ void pci_init_board(void)
#endif /* CONFIG_PCISLAVE */
#if defined(CONFIG_OF_LIBFDT)
-void
-ft_pci_setup(void *blob, bd_t *bd)
+void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
- int err;
int tmp[2];
+ const char *path;
- nodeoffset = fdt_path_offset(blob, "/" OF_SOC "/pci@8500");
+ nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
- tmp[0] = cpu_to_be32(hose[0].first_busno);
- tmp[1] = cpu_to_be32(hose[0].last_busno);
- err = fdt_setprop(blob, nodeoffset, "bus-range",
- tmp, sizeof(tmp));
-
- tmp[0] = cpu_to_be32(gd->pci_clk);
- err = fdt_setprop(blob, nodeoffset, "clock-frequency",
- tmp, sizeof(tmp[0]));
- }
-}
-#elif defined(CONFIG_OF_FLAT_TREE)
-void
-ft_pci_setup(void *blob, bd_t *bd)
-{
- u32 *p;
- int len;
-
- p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
- if (p != NULL) {
- p[0] = hose[0].first_busno;
- p[1] = hose[0].last_busno;
+ path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+ if (path) {
+ tmp[0] = cpu_to_be32(hose[0].first_busno);
+ tmp[1] = cpu_to_be32(hose[0].last_busno);
+ do_fixup_by_path(blob, path, "bus-range",
+ &tmp, sizeof(tmp), 1);
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ do_fixup_by_path(blob, path, "clock-frequency",
+ &tmp, sizeof(tmp[0]), 1);
+ }
}
}
-#endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_OF_LIBFDT */
#endif /* CONFIG_PCI */