diff options
Diffstat (limited to 'board/freescale/mpc8315erdb')
| -rw-r--r-- | board/freescale/mpc8315erdb/mpc8315erdb.c | 28 | ||||
| -rw-r--r-- | board/freescale/mpc8315erdb/sdram.c | 34 |
2 files changed, 31 insertions, 31 deletions
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index 0330218..ea4b04f 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) { - volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) gd->flags |= GD_FLG_SILENT; @@ -48,7 +48,7 @@ static u8 read_board_info(void) u8 val8; i2c_set_bus_num(0); - if (i2c_read(CFG_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) + if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) return val8; else return 0; @@ -76,28 +76,28 @@ int checkboard(void) static struct pci_region pci_regions[] = { { - bus_start: CFG_PCI_MEM_BASE, - phys_start: CFG_PCI_MEM_PHYS, - size: CFG_PCI_MEM_SIZE, + bus_start: CONFIG_SYS_PCI_MEM_BASE, + phys_start: CONFIG_SYS_PCI_MEM_PHYS, + size: CONFIG_SYS_PCI_MEM_SIZE, flags: PCI_REGION_MEM | PCI_REGION_PREFETCH }, { - bus_start: CFG_PCI_MMIO_BASE, - phys_start: CFG_PCI_MMIO_PHYS, - size: CFG_PCI_MMIO_SIZE, + bus_start: CONFIG_SYS_PCI_MMIO_BASE, + phys_start: CONFIG_SYS_PCI_MMIO_PHYS, + size: CONFIG_SYS_PCI_MMIO_SIZE, flags: PCI_REGION_MEM }, { - bus_start: CFG_PCI_IO_BASE, - phys_start: CFG_PCI_IO_PHYS, - size: CFG_PCI_IO_SIZE, + bus_start: CONFIG_SYS_PCI_IO_BASE, + phys_start: CONFIG_SYS_PCI_IO_PHYS, + size: CONFIG_SYS_PCI_IO_SIZE, flags: PCI_REGION_IO } }; void pci_init_board(void) { - volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions }; @@ -109,10 +109,10 @@ void pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c index 07e6486..ead7b1e 100644 --- a/board/freescale/mpc8315erdb/sdram.c +++ b/board/freescale/mpc8315erdb/sdram.c @@ -56,13 +56,13 @@ static void resume_from_sleep(void) */ static long fixed_sdram(void) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - u32 msize = CFG_DDR_SIZE * 1024 * 1024; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); - im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1); - im->sysconf.ddrcdr = CFG_DDRCDR_VALUE; + im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE; /* * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], @@ -71,27 +71,27 @@ static long fixed_sdram(void) udelay(50000); im->ddr.csbnds[0].csbnds = (msize - 1) >> 24; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; /* Currently we use only one CS, so disable the other bank. */ im->ddr.cs_config[1] = 0; - im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG | SDRAM_CFG_BI; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI; else - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; sync(); /* enable DDR controller */ @@ -103,7 +103,7 @@ static long fixed_sdram(void) phys_size_t initdram(int board_type) { - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |