diff options
Diffstat (limited to 'board/freescale/ls2080ardb')
-rw-r--r-- | board/freescale/ls2080ardb/MAINTAINERS | 2 | ||||
-rw-r--r-- | board/freescale/ls2080ardb/README | 45 | ||||
-rw-r--r-- | board/freescale/ls2080ardb/ddr.h | 32 | ||||
-rw-r--r-- | board/freescale/ls2080ardb/eth_ls2080rdb.c | 5 | ||||
-rw-r--r-- | board/freescale/ls2080ardb/ls2080ardb.c | 6 |
5 files changed, 31 insertions, 59 deletions
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS index 5562917..a20c003 100644 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -1,5 +1,5 @@ LS2080A BOARD -M: Prabhakar Kushwaha <prabhakar@freescale.com> +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> S: Maintained F: board/freescale/ls2080ardb/ F: board/freescale/ls2080a/ls2080ardb.c diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README index 6708ca9..b1613ba 100644 --- a/board/freescale/ls2080ardb/README +++ b/board/freescale/ls2080ardb/README @@ -5,48 +5,9 @@ evaluation, and development platform that supports the QorIQ LS2080A Layerscape Architecture processor. LS2080A SoC Overview ------------------- -The LS2080A integrated multicore processor combines eight ARM Cortex-A57 -processor cores with high-performance data path acceleration logic and network -and peripheral bus interfaces required for networking, telecom/datacom, -wireless infrastructure, and mil/aerospace applications. - -The LS2080A SoC includes the following function and features: - - - Eight 64-bit ARM Cortex-A57 CPUs - - 1 MB platform cache with ECC - - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support - - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by - the AIOP - - Data path acceleration architecture (DPAA2) incorporating acceleration for - the following functions: - - Packet parsing, classification, and distribution (WRIOP) - - Queue and Hardware buffer management for scheduling, packet sequencing, and - congestion management, buffer allocation and de-allocation (QBMan) - - Cryptography acceleration (SEC) at up to 10 Gbps - - RegEx pattern matching acceleration (PME) at up to 10 Gbps - - Decompression/compression acceleration (DCE) at up to 20 Gbps - - Accelerated I/O processing (AIOP) at up to 20 Gbps - - QDMA engine - - 16 SerDes lanes at up to 10.3125 GHz - - Ethernet interfaces - - Up to eight 10 Gbps Ethernet MACs - - Up to eight 1 / 2.5 Gbps Ethernet MACs - - High-speed peripheral interfaces - - Four PCIe 3.0 controllers, one supporting SR-IOV - - Additional peripheral interfaces - - Two serial ATA (SATA 3.0) controllers - - Two high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Serial peripheral interface (SPI) controller - - Quad Serial Peripheral Interface (QSPI) Controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash - - Support for hardware virtualization and partitioning enforcement - - QorIQ platform's trust architecture 3.0 - - Service processor (SP) provides pre-boot initialization and secure-boot - capabilities +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. LS2080ARDB board Overview ----------------------- diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h index bda9d4a..8d5a490 100644 --- a/board/freescale/ls2080ardb/ddr.h +++ b/board/freescale/ls2080ardb/ddr.h @@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 8, 0x08090B0D, 0x0E10100C,}, - {2, 1900, 0, 4, 8, 0x090A0C0E, 0x1012120D,}, - {2, 2300, 0, 4, 9, 0x0A0B0C10, 0x1114140E,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,}, + {2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,}, + {2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,}, {} }; @@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, - {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, {} }; @@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; @@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index 58ea746..799799c 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -20,9 +20,11 @@ DECLARE_GLOBAL_DATA_PTR; +#define MC_BOOT_ENV_VAR "mcinitcmd" int board_eth_init(bd_t *bis) { #if defined(CONFIG_FSL_MC_ENET) + char *mc_boot_env_var; int i, interface; struct memac_mdio_info mdio_info; struct mii_dev *dev; @@ -89,6 +91,9 @@ int board_eth_init(bd_t *bis) } } + mc_boot_env_var = getenv(MC_BOOT_ENV_VAR); + if (mc_boot_env_var) + run_command_list(mc_boot_env_var, -1, 0); cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index fb39af6..52e5e3f 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -156,7 +156,9 @@ int board_init(void) { char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; +#ifdef CONFIG_FSL_MC_ENET u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; +#endif u32 val; init_final_memctl_regs(); @@ -178,8 +180,10 @@ int board_init(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); +#ifdef CONFIG_FSL_MC_ENET /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); +#endif return 0; } @@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_FSL_MC_ENET int err; +#endif u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; |