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-rw-r--r--board/freescale/ls1021aqds/ls1021aqds.c21
1 files changed, 14 insertions, 7 deletions
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 691e993..f2dda22 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -197,6 +197,20 @@ int board_early_init_f(void)
out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
#endif
+ /*
+ * Enable snoop requests and DVM message requests for
+ * Slave insterface S4 (A7 core cluster)
+ */
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ /*
+ * Set CCI-400 Slave interface S1, S2 Shareable Override Register
+ * All transactions are treated as non-shareable
+ */
+ out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
/* Workaround for the issue that DDR could not respond to
* barrier transaction which is generated by executing DSB/ISB
* instruction. Set CCI-400 control override register to
@@ -508,13 +522,6 @@ int board_init(void)
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
- /*
- * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
- * All transactions are treated as non-shareable
- */
- out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);