diff options
Diffstat (limited to 'board/exbitgen')
| -rw-r--r-- | board/exbitgen/exbitgen.c | 22 | ||||
| -rw-r--r-- | board/exbitgen/init.S | 14 |
2 files changed, 18 insertions, 18 deletions
diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c index 0f84127..50d9748 100644 --- a/board/exbitgen/exbitgen.c +++ b/board/exbitgen/exbitgen.c @@ -37,13 +37,13 @@ int board_early_init_f (void) | +-------------------------------------------------------------------------*/ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */ - mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ + mtdcr (UIC0CR, 0x00000020); /* set all but FPGA SMI to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF90); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ /* Perform reset of PHY connected to PPC via register in CPLD */ out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */ @@ -94,28 +94,28 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S index c2dae56..7a9726f 100644 --- a/board/exbitgen/init.S +++ b/board/exbitgen/init.S @@ -382,7 +382,7 @@ sdram_init: /*----------------------------------------------------------- */ /* Set SDTR1 */ /*----------------------------------------------------------- */ - addi r5,0,mem_sdtr1 + addi r5,0,SDRAM0_TR mtdcr SDRAM0_CFGADDR,r5 mtdcr SDRAM0_CFGDATA,r4 @@ -413,7 +413,7 @@ sdram_init: /* Set SDRAM bank 0 register and adjust r6 for next bank */ /*------------------------------------------------------ */ - addi r7,0,mem_mb0cf + addi r7,0,SDRAM0_B0CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 @@ -424,7 +424,7 @@ sdram_init: cmpi 0, r12, 2 bne b1skip - addi r7,0,mem_mb1cf + addi r7,0,SDRAM0_B1CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 @@ -432,7 +432,7 @@ sdram_init: /* Set SDRAM bank 2 register and adjust r6 for next bank */ /*------------------------------------------------------ */ -b1skip: addi r7,0,mem_mb2cf +b1skip: addi r7,0,SDRAM0_B2CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 @@ -443,7 +443,7 @@ b1skip: addi r7,0,mem_mb2cf cmpi 0, r12, 2 bne b3skip - addi r7,0,mem_mb3cf + addi r7,0,SDRAM0_B3CR mtdcr SDRAM0_CFGADDR,r7 mtdcr SDRAM0_CFGDATA,r6 b3skip: @@ -456,7 +456,7 @@ b3skip: addis r7, 0, 0x05F0 /* RTR value for 100Mhz */ bl rtr_2 rtr_1: addis r7, 0, 0x03F8 -rtr_2: addi r4,0,mem_rtr +rtr_2: addi r4,0,SDRAM0_RTR mtdcr SDRAM0_CFGADDR,r4 mtdcr SDRAM0_CFGDATA,r7 @@ -476,7 +476,7 @@ rtr_2: addi r4,0,mem_rtr /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ /* read/prefetch. */ /*----------------------------------------------------------- */ - addi r4,0,mem_mcopt1 + addi r4,0,SDRAM0_CFG mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x80C0 /* set DC_EN=1 */ ori r4,r4,0x0000 |