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-rw-r--r--board/etin/debris/debris.c12
-rw-r--r--board/etin/debris/flash.c12
-rw-r--r--board/etin/debris/phantom.c6
-rw-r--r--board/etin/kvme080/kvme080.c36
4 files changed, 40 insertions, 26 deletions
diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c
index 763760f..227c49a 100644
--- a/board/etin/debris/debris.c
+++ b/board/etin/debris/debris.c
@@ -25,6 +25,7 @@
#include <mpc824x.h>
#include <pci.h>
#include <i2c.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -62,7 +63,7 @@ phys_size_t initdram (int board_type)
uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
uint8_t mber = 0;
- i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */
m = i2c_reg_read (0x50, 5); /* # of physical banks */
@@ -73,7 +74,7 @@ phys_size_t initdram (int board_type)
CONFIG_READ_WORD(MCCR1, mccr1);
mccr1 &= 0xffff0000;
- start = CFG_SDRAM_BASE;
+ start = CONFIG_SYS_SDRAM_BASE;
end = start + (1 << (col + row + 3) ) * bank - 1;
for (i = 0; i < m; i++) {
@@ -173,7 +174,12 @@ void nvram_write(long dest, const void *src, size_t count)
int misc_init_r(void)
{
/* Write ethernet addr in NVRAM for VxWorks */
- nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS,
+ nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS,
(char*)&gd->bd->bi_enetaddr[0], 6);
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/board/etin/debris/flash.c b/board/etin/debris/flash.c
index a4100e5..a3c8138 100644
--- a/board/etin/debris/flash.c
+++ b/board/etin/debris/flash.c
@@ -71,7 +71,7 @@ static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr)
return (uint16_t)read32(base + addr);
}
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
static void move64(uint64_t *src, uint64_t *dest)
{
@@ -99,7 +99,7 @@ static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data)
status &= CMD(0x80);
if(status == CMD(0x80))
break;
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
cfi_cmd(flash, 0xff, 0);
return 1;
}
@@ -128,7 +128,7 @@ static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data)
start = get_timer (0);
status = ~data;
while(status != data) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
return 1;
status = cfi_read(flash, dest);
udelay(1);
@@ -230,7 +230,7 @@ static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect)
status &= CMD(0x80);
if (status == CMD(0x80))
break;
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
cfi_cmd(flash, 0xff, 0);
printf ("Timeout\n");
return ERR_TIMOUT;
@@ -296,7 +296,7 @@ static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
if (status == CMD(0xffff))
break;
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return ERR_TIMOUT;
}
@@ -581,7 +581,7 @@ unsigned long flash_init (void)
mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
set_msr(msr);
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
flash_info[i].flash_id = FLASH_UNKNOWN;
size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]);
if (!size)
diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c
index 263da6b..fcb4c40 100644
--- a/board/etin/debris/phantom.c
+++ b/board/etin/debris/phantom.c
@@ -20,7 +20,7 @@
#if defined(CONFIG_CMD_DATE)
-#define RTC_BASE (CFG_NVRAM_BASE_ADDR + 0x7fff8)
+#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8)
#define RTC_YEAR ( RTC_BASE + 7 )
#define RTC_MONTH ( RTC_BASE + 6 )
@@ -254,7 +254,7 @@ int rtc_get( struct rtc_time *tmp)
return 0;
}
-void rtc_set( struct rtc_time *tmp )
+int rtc_set( struct rtc_time *tmp )
{
if (phantom_flag < 0)
phantom_flag = get_phantom_flag();
@@ -307,6 +307,8 @@ void rtc_set( struct rtc_time *tmp )
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
}
+
+ return 0;
}
#endif
diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c
index bfd6854..8c6afc9 100644
--- a/board/etin/kvme080/kvme080.c
+++ b/board/etin/kvme080/kvme080.c
@@ -25,6 +25,7 @@
#include <mpc824x.h>
#include <pci.h>
#include <i2c.h>
+#include <netdev.h>
#include <asm/processor.h>
int checkboard(void)
@@ -45,7 +46,7 @@ unsigned long setdram(int m, int row, int col, int bank)
CONFIG_READ_WORD(MCCR1, mccr1);
mccr1 &= 0xffff0000;
- start = CFG_SDRAM_BASE;
+ start = CONFIG_SYS_SDRAM_BASE;
end = start + (1 << (col + row + 3) ) * bank - 1;
for (i = 0; i < m; i++) {
@@ -100,31 +101,31 @@ phys_size_t initdram(int board_type)
msr = mfmsr();
mtmsr(msr & ~(MSR_IR | MSR_DR));
- mtspr(IBAT2L, CFG_IBAT0L + 0x10000000);
- mtspr(IBAT2U, CFG_IBAT0U + 0x10000000);
- mtspr(DBAT2L, CFG_DBAT0L + 0x10000000);
- mtspr(DBAT2U, CFG_DBAT0U + 0x10000000);
+ mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
+ mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
+ mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
+ mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
mtmsr(msr);
- if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000))
+ if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
size = 0x20000000; /* 512MB */
- else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
+ else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
size = 0x10000000; /* 256MB */
- else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
+ else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
size = 0x10000000; /* 256MB */
- else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
+ else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
size = 0x08000000; /* 128MB */
- else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
+ else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
size = 0x08000000; /* 128MB */
- else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000))
+ else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
size = 0x04000000; /* 64MB */
msr = mfmsr();
mtmsr(msr & ~(MSR_IR | MSR_DR));
- mtspr(IBAT2L, CFG_IBAT2L);
- mtspr(IBAT2U, CFG_IBAT2U);
- mtspr(DBAT2L, CFG_DBAT2L);
- mtspr(DBAT2U, CFG_DBAT2U);
+ mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
+ mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
+ mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
+ mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
mtmsr(msr);
return size;
@@ -191,3 +192,8 @@ void nvram_write(long dest, const void *src, size_t count)
asm volatile("sync");
}
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
generated by cgit v1.1 at 2024-11-18 22:46:34 +0000