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-rw-r--r--board/esd/adciop/adciop.c6
-rw-r--r--board/esd/adciop/flash.c2
-rw-r--r--board/esd/adciop/u-boot.lds1
-rw-r--r--board/esd/apc405/apc405.c68
-rw-r--r--board/esd/apc405/u-boot.lds3
-rw-r--r--board/esd/ar405/flash.c4
-rw-r--r--board/esd/ar405/u-boot.lds8
-rw-r--r--board/esd/ash405/ash405.c31
-rw-r--r--board/esd/ash405/flash.c4
-rw-r--r--board/esd/ash405/u-boot.lds3
-rw-r--r--board/esd/canbt/flash.c2
-rw-r--r--board/esd/canbt/u-boot.lds4
-rw-r--r--board/esd/cms700/cms700.c51
-rw-r--r--board/esd/cms700/flash.c4
-rw-r--r--board/esd/cms700/u-boot.lds3
-rw-r--r--board/esd/common/auto_update.c6
-rw-r--r--board/esd/common/cmd_loadpci.c24
-rw-r--r--board/esd/common/esd405ep_nand.c18
-rw-r--r--board/esd/common/flash.c136
-rw-r--r--board/esd/common/fpga.c18
-rw-r--r--board/esd/common/lcd.c34
-rw-r--r--board/esd/common/pci.c22
-rw-r--r--board/esd/common/xilinx_jtag/ports.h10
-rw-r--r--board/esd/cpci2dp/cpci2dp.c49
-rw-r--r--board/esd/cpci2dp/flash.c2
-rw-r--r--board/esd/cpci2dp/u-boot.lds3
-rw-r--r--board/esd/cpci405/config.mk16
-rw-r--r--board/esd/cpci405/cpci405.c77
-rw-r--r--board/esd/cpci405/flash.c2
-rw-r--r--board/esd/cpci405/u-boot.lds16
-rw-r--r--board/esd/cpci5200/cpci5200.c20
-rw-r--r--board/esd/cpci5200/strataflash.c22
-rw-r--r--board/esd/cpci750/cpci750.c134
-rw-r--r--board/esd/cpci750/i2c.c8
-rw-r--r--board/esd/cpci750/ide.c8
-rw-r--r--board/esd/cpci750/local.h2
-rw-r--r--board/esd/cpci750/misc.S26
-rw-r--r--board/esd/cpci750/mpsc.c6
-rw-r--r--board/esd/cpci750/pci.c26
-rw-r--r--board/esd/cpci750/sdram_init.c8
-rw-r--r--board/esd/cpci750/u-boot.lds3
-rw-r--r--board/esd/cpciiser4/cpciiser4.c19
-rw-r--r--board/esd/cpciiser4/flash.c2
-rw-r--r--board/esd/cpciiser4/u-boot.lds3
-rw-r--r--board/esd/dasa_sim/cmd_dasa_sim.c14
-rw-r--r--board/esd/dasa_sim/dasa_sim.c16
-rw-r--r--board/esd/dasa_sim/flash.c2
-rw-r--r--board/esd/dasa_sim/u-boot.lds4
-rw-r--r--board/esd/dp405/dp405.c36
-rw-r--r--board/esd/dp405/flash.c4
-rw-r--r--board/esd/dp405/u-boot.lds5
-rw-r--r--board/esd/du405/du405.c15
-rw-r--r--board/esd/du405/flash.c2
-rw-r--r--board/esd/du405/u-boot.lds3
-rw-r--r--board/esd/du440/config.mk2
-rw-r--r--board/esd/du440/du440.c173
-rw-r--r--board/esd/du440/du440.h20
-rw-r--r--board/esd/du440/init.S26
-rw-r--r--board/esd/du440/u-boot.lds3
-rw-r--r--board/esd/hh405/flash.c4
-rw-r--r--board/esd/hh405/hh405.c103
-rw-r--r--board/esd/hh405/u-boot.lds3
-rw-r--r--board/esd/hub405/flash.c4
-rw-r--r--board/esd/hub405/hub405.c32
-rw-r--r--board/esd/hub405/u-boot.lds5
-rw-r--r--board/esd/mecp5200/mecp5200.c22
-rw-r--r--board/esd/ocrtc/flash.c2
-rw-r--r--board/esd/ocrtc/ocrtc.c32
-rw-r--r--board/esd/ocrtc/u-boot.lds3
-rw-r--r--board/esd/pci405/cmd_pci405.c871
-rw-r--r--board/esd/pci405/flash.c2
-rw-r--r--board/esd/pci405/pci405.c88
-rw-r--r--board/esd/pci405/u-boot.lds3
-rw-r--r--board/esd/pf5200/flash.c32
-rw-r--r--board/esd/pf5200/pf5200.c24
-rw-r--r--board/esd/plu405/config.mk3
-rw-r--r--board/esd/plu405/flash.c4
-rw-r--r--board/esd/plu405/plu405.c88
-rw-r--r--board/esd/plu405/u-boot.lds15
-rw-r--r--board/esd/pmc405/pmc405.c54
-rw-r--r--board/esd/pmc405/u-boot.lds3
-rw-r--r--board/esd/pmc440/cmd_pmc440.c84
-rw-r--r--board/esd/pmc440/config.mk2
-rw-r--r--board/esd/pmc440/fpga.c5
-rw-r--r--board/esd/pmc440/init.S26
-rw-r--r--board/esd/pmc440/pmc440.c204
-rw-r--r--board/esd/pmc440/pmc440.h21
-rw-r--r--board/esd/pmc440/sdram.c2
-rw-r--r--board/esd/pmc440/u-boot-nand.lds3
-rw-r--r--board/esd/pmc440/u-boot.lds3
-rw-r--r--board/esd/tasreg/flash.c8
-rw-r--r--board/esd/tasreg/tasreg.c16
-rw-r--r--board/esd/tasreg/u-boot.lds2
-rw-r--r--board/esd/voh405/flash.c4
-rw-r--r--board/esd/voh405/u-boot.lds5
-rw-r--r--board/esd/voh405/voh405.c98
-rw-r--r--board/esd/vom405/flash.c4
-rw-r--r--board/esd/vom405/u-boot.lds13
-rw-r--r--board/esd/vom405/vom405.c25
-rw-r--r--board/esd/wuh405/flash.c4
-rw-r--r--board/esd/wuh405/u-boot.lds3
-rw-r--r--board/esd/wuh405/wuh405.c29
102 files changed, 1023 insertions, 2174 deletions
diff --git a/board/esd/adciop/adciop.c b/board/esd/adciop/adciop.c
index 0f655b7..63aaf2c 100644
--- a/board/esd/adciop/adciop.c
+++ b/board/esd/adciop/adciop.c
@@ -22,6 +22,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include "adciop.h"
/* ------------------------------------------------------------------------- */
@@ -95,3 +96,8 @@ int testdram (void)
}
/* ------------------------------------------------------------------------- */
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/board/esd/adciop/flash.c b/board/esd/adciop/flash.c
index d9eccba..dd578c8 100644
--- a/board/esd/adciop/flash.c
+++ b/board/esd/adciop/flash.c
@@ -45,7 +45,7 @@ unsigned long flash_init (void)
int i;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
diff --git a/board/esd/adciop/u-boot.lds b/board/esd/adciop/u-boot.lds
index db65fe6..e918163 100644
--- a/board/esd/adciop/u-boot.lds
+++ b/board/esd/adciop/u-boot.lds
@@ -132,6 +132,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
index 83657c8..ac9bbb3 100644
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -41,7 +41,7 @@ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);
extern ulong flash_get_size (ulong base, int banknum);
-int flash_banks = CFG_MAX_FLASH_BANKS_DETECT;
+int flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
/* fpga configuration data - gzip compressed and generated by bin2c */
const unsigned char fpgadata[] =
@@ -140,7 +140,7 @@ int board_early_init_f (void)
* First pull fpga-prg pin low, to disable fpga logic
*/
out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
- out_be32((void*)GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
+ out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
out_be32((void*)GPIO0_OR, 0); /* pull prg low */
/*
@@ -178,8 +178,8 @@ int board_early_init_f (void)
mtebc(pb1cr, 0);
/* resize CS0 to 32MB */
- mtebc(pb0ap, CFG_EBC_PB0AP_HWREV8);
- mtebc(pb0cr, CFG_EBC_PB0CR_HWREV8);
+ mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP_HWREV8);
+ mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR_HWREV8);
}
return 0;
@@ -200,8 +200,8 @@ int board_early_init_r(void)
int misc_init_r(void)
{
- u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
- u16 *fpga_ctrl2 =(u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
+ u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+ u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
unsigned char *dst;
@@ -222,8 +222,8 @@ int misc_init_r(void)
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00300000);
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf("GUNZIP ERROR - must RESET board to recover\n");
do_reset(NULL, 0, 0, NULL);
}
@@ -297,11 +297,11 @@ int misc_init_r(void)
/*
* Enable power on PS/2 interface (with reset)
*/
- out_be16(fpga_mode, in_be16(fpga_mode) | CFG_FPGA_CTRL_PS2_RESET);
+ out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
for (i=0;i<100;i++)
udelay(1000);
udelay(1000);
- out_be16(fpga_mode, in_be16(fpga_mode) & ~CFG_FPGA_CTRL_PS2_RESET);
+ out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
/*
* Enable interrupts in exar duart mcr[3]
@@ -315,15 +315,15 @@ int misc_init_r(void)
str = getenv("splashimage");
if (str) {
logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
- logo_size = CFG_VIDEO_LOGO_MAX_SIZE;
+ logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
} else {
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
}
if (gd->board_type >= 6) {
- result = lcd_init((uchar *)CFG_LCD_BIG_REG,
- (uchar *)CFG_LCD_BIG_MEM,
+ result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13505_640_480_16bpp,
sizeof(regs_13505_640_480_16bpp) /
sizeof(regs_13505_640_480_16bpp[0]),
@@ -332,16 +332,16 @@ int misc_init_r(void)
/* retry with internal image */
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
- lcd_init((uchar *)CFG_LCD_BIG_REG,
- (uchar *)CFG_LCD_BIG_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13505_640_480_16bpp,
sizeof(regs_13505_640_480_16bpp) /
sizeof(regs_13505_640_480_16bpp[0]),
logo_addr, logo_size);
}
} else {
- result = lcd_init((uchar *)CFG_LCD_BIG_REG,
- (uchar *)CFG_LCD_BIG_MEM,
+ result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp) /
sizeof(regs_13806_640_480_16bpp[0]),
@@ -350,8 +350,8 @@ int misc_init_r(void)
/* retry with internal image */
logo_addr = logo_bmp;
logo_size = sizeof(logo_bmp);
- lcd_init((uchar *)CFG_LCD_BIG_REG,
- (uchar *)CFG_LCD_BIG_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+ (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp) /
sizeof(regs_13806_640_480_16bpp[0]),
@@ -389,12 +389,12 @@ int misc_init_r(void)
* fix environment for field updated units
*/
if (getenv("altbootcmd") == NULL) {
- setenv("usb_load", CFG_USB_LOAD_COMMAND);
- setenv("usbargs", CFG_USB_ARGS);
+ setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
+ setenv("usbargs", CONFIG_SYS_USB_ARGS);
setenv("bootcmd", CONFIG_BOOTCOMMAND);
- setenv("usb_self", CFG_USB_SELF_COMMAND);
- setenv("bootlimit", CFG_BOOTLIMIT);
- setenv("altbootcmd", CFG_ALT_BOOTCOMMAND);
+ setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
+ setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
+ setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
saveenv();
}
@@ -423,30 +423,20 @@ int checkboard (void)
return 0;
}
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
- u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) {
out_be16(fpga_mode,
- in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET);
+ in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else {
out_be16(fpga_mode,
- in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET);
+ in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
}
}
#endif /* CONFIG_IDE_RESET */
@@ -459,7 +449,7 @@ void reset_phy(void)
lxt971_no_sleep();
}
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
int usb_board_init(void)
{
return 0;
@@ -490,4 +480,4 @@ int usb_board_init_fail(void)
usb_board_stop();
return 0;
}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
diff --git a/board/esd/apc405/u-boot.lds b/board/esd/apc405/u-boot.lds
index 21547ac..9697cc6 100644
--- a/board/esd/apc405/u-boot.lds
+++ b/board/esd/apc405/u-boot.lds
@@ -72,7 +72,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -143,6 +143,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/ar405/flash.c
+++ b/board/esd/ar405/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -91,7 +91,7 @@ unsigned long flash_init (void)
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
diff --git a/board/esd/ar405/u-boot.lds b/board/esd/ar405/u-boot.lds
index b072bbb..2c1cf92 100644
--- a/board/esd/ar405/u-boot.lds
+++ b/board/esd/ar405/u-boot.lds
@@ -66,7 +66,7 @@ SECTIONS
cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/4xx_enet.o (.text)
+ drivers/net/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
@@ -79,14 +79,13 @@ SECTIONS
common/cmd_mem.o (.text)
common/cmd_nvedit.o (.text)
common/console.o (.text)
- common/lists.o (.text)
common/main.o (.text)
/*
. = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.ppcenv)
+ common/env_embedded.o (.ppcenv)
*/
- common/environment.o (.text)
+ common/env_embedded.o (.text)
*(.text)
*(.fixup)
@@ -157,6 +156,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c
index 25360a6..dd1e2ec 100644
--- a/board/esd/ash405/ash405.c
+++ b/board/esd/ash405/ash405.c
@@ -82,15 +82,6 @@ int board_early_init_f (void)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
@@ -103,8 +94,8 @@ int misc_init_r (void)
int index;
int i;
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
@@ -166,9 +157,9 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
udelay(10); /* wait 10us */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
udelay(1000); /* wait 1ms */
/*
@@ -205,20 +196,6 @@ int checkboard (void)
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/ash405/flash.c
+++ b/board/esd/ash405/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -91,7 +91,7 @@ unsigned long flash_init (void)
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
diff --git a/board/esd/ash405/u-boot.lds b/board/esd/ash405/u-boot.lds
index 644174a..e2e2512 100644
--- a/board/esd/ash405/u-boot.lds
+++ b/board/esd/ash405/u-boot.lds
@@ -72,7 +72,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -142,6 +142,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c
index de847f9..56c822e 100644
--- a/board/esd/canbt/flash.c
+++ b/board/esd/canbt/flash.c
@@ -47,7 +47,7 @@ unsigned long flash_init (void)
unsigned long base_b0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
diff --git a/board/esd/canbt/u-boot.lds b/board/esd/canbt/u-boot.lds
index e66db5d..74280e6 100644
--- a/board/esd/canbt/u-boot.lds
+++ b/board/esd/canbt/u-boot.lds
@@ -78,12 +78,11 @@ SECTIONS
common/cmd_mem.o (.text)
common/cmd_nvedit.o (.text)
common/console.o (.text)
- common/lists.o (.text)
common/main.o (.text)
net/net.o (.text)
/* . = env_offset;
- common/environment.o (.text)
+ common/env_embedded.o (.text)
*/
*(.text)
@@ -155,6 +154,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index ba27c03..5709d45 100644
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -69,23 +69,14 @@ int board_early_init_f (void)
/*
* Reset CPLD via GPIO12 (CS3) pin
*/
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
udelay(1000); /* wait 1ms */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
udelay(1000); /* wait 1ms */
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
/* adjust flash start and offset */
@@ -95,7 +86,7 @@ int misc_init_r (void)
/*
* Setup and enable EEPROM write protection
*/
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
return (0);
}
@@ -110,8 +101,8 @@ int checkboard (void)
char str[64];
int flashcnt;
int delay;
- volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);
- volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001);
+ volatile unsigned char *led_reg = (unsigned char *)((ulong)CONFIG_SYS_PLD_BASE + 0x1000);
+ volatile unsigned char *ver_reg = (unsigned char *)((ulong)CONFIG_SYS_PLD_BASE + 0x1001);
puts ("Board: ");
@@ -141,19 +132,7 @@ int checkboard (void)
/* ------------------------------------------------------------------------- */
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
* 0: disable write
@@ -164,23 +143,23 @@ phys_size_t initdram (int board_type)
*/
int eeprom_write_enable (unsigned dev_addr, int state)
{
- if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
return -1;
} else {
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
+ state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
break;
}
}
@@ -194,21 +173,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (query) {
/* Query write access state. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0) {
puts ("Query of write access state failed.\n");
} else {
printf ("Write access for device 0x%0x is %sabled.\n",
- CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
} else {
/* Enable write access. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
}
if (state < 0) {
puts ("Setup of write access state failed.\n");
@@ -221,7 +200,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
"eepwren - Enable / disable / query EEPROM write access\n",
NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
/* ------------------------------------------------------------------------- */
diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c
index 89af119..274ada9 100644
--- a/board/esd/cms700/flash.c
+++ b/board/esd/cms700/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -91,7 +91,7 @@ unsigned long flash_init (void)
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
diff --git a/board/esd/cms700/u-boot.lds b/board/esd/cms700/u-boot.lds
index 21547ac..9697cc6 100644
--- a/board/esd/cms700/u-boot.lds
+++ b/board/esd/cms700/u-boot.lds
@@ -72,7 +72,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -143,6 +143,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index a1e0ce5..633f641 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -72,7 +72,7 @@ extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs,
size_t len, int clean);
#endif
-extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE];
+extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
int au_check_cksum_valid(int i, long nbytes)
{
@@ -335,7 +335,7 @@ static void process_macros (const char *input, char *output)
char c, prev;
const char *varname_start = NULL;
int inputcnt = strlen (input);
- int outputcnt = CFG_CBSIZE;
+ int outputcnt = CONFIG_SYS_CBSIZE;
int state = 0; /* 0 = waiting for '$' */
/* 1 = waiting for '(' or '{' */
/* 2 = waiting for ')' or '}' */
@@ -394,7 +394,7 @@ static void process_macros (const char *input, char *output)
case 2: /* Waiting for ) */
if (c == ')' || c == '}') {
int i;
- char envname[CFG_CBSIZE], *envval;
+ char envname[CONFIG_SYS_CBSIZE], *envval;
/* Varname # of chars */
int envcnt = input - varname_start - 1;
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
index d88b387..ad490c3 100644
--- a/board/esd/common/cmd_loadpci.c
+++ b/board/esd/common/cmd_loadpci.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2008
* Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
@@ -23,6 +23,9 @@
#include <common.h>
#include <command.h>
+#if !defined(CONFIG_440)
+#include <asm/4xx_pci.h>
+#endif
#if defined(CONFIG_CMD_BSP)
@@ -36,18 +39,24 @@ extern int do_autoscript (cmd_tbl_t *, int, int, char *[]);
*/
int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- unsigned int *ptr = 0;
+ u32 *ptr = 0;
int count = 0;
int count2 = 0;
char addr[16];
char str[] = "\\|/-";
char *local_args[2];
+ u32 la, ptm1la;
+#if defined(CONFIG_440)
+ ptm1la = in32r(PCIX0_PTM1LA);
+#else
+ ptm1la = in32r(PTM1LA);
+#endif
while(1) {
/*
* Mark sync address
*/
- ptr = 0;
+ ptr = (u32 *)ptm1la;
memset(ptr, 0, 0x20);
*ptr = 0xffffffff;
@@ -74,7 +83,8 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
printf("\nGot bootcode %08x: ", *ptr);
- sprintf(addr, "%08x", *ptr & ADDRMASK);
+ la = ptm1la + (*ptr & ADDRMASK);
+ sprintf(addr, "%08x", la);
switch (*ptr & ~ADDRMASK) {
case 0:
@@ -83,8 +93,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
*/
printf("booting image at addr 0x%s ...\n", addr);
setenv("loadaddr", addr);
-
- do_bootm (cmdtp, 0, 0, NULL);
+ do_bootm(cmdtp, 0, 0, NULL);
break;
case 1:
@@ -92,7 +101,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
* Boot image via autoscr
*/
printf("executing script at addr 0x%s ...\n", addr);
-
local_args[0] = addr;
local_args[1] = NULL;
do_autoscript(cmdtp, 0, 1, local_args);
@@ -103,7 +111,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
* Call run_cmd
*/
printf("running command at addr 0x%s ...\n", addr);
- run_command ((char*)(*ptr & ADDRMASK), 0);
+ run_command((char*)la, 0);
break;
default:
diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c
index 40d1efb..736176f 100644
--- a/board/esd/common/esd405ep_nand.c
+++ b/board/esd/common/esd405ep_nand.c
@@ -35,17 +35,17 @@ static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int
struct nand_chip *this = mtd->priv;
if (ctrl & NAND_CTRL_CHANGE) {
if ( ctrl & NAND_CLE )
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
else
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);
if ( ctrl & NAND_ALE )
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE);
else
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);
if ( ctrl & NAND_NCE )
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE);
else
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
}
if (cmd != NAND_CMD_NONE)
@@ -58,7 +58,7 @@ static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int
*/
static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
{
- if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY)
+ if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY)
return 1;
return 0;
}
@@ -69,8 +69,8 @@ int board_nand_init(struct nand_chip *nand)
/*
* Set NAND-FLASH GPIO signals to defaults
*/
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+ out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
/*
* Initialize nand_chip structure
diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c
index bda361e..3ea053b 100644
--- a/board/esd/common/flash.c
+++ b/board/esd/common/flash.c
@@ -27,7 +27,7 @@
#endif
#include <asm/processor.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
@@ -167,7 +167,7 @@ void flash_print_info (flash_info_t *info)
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
-#ifdef CFG_FLASH_EMPTY_INFO
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
/*
* Check if whole sector is erased
*/
@@ -221,28 +221,28 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
short n;
- CFG_FLASH_WORD_SIZE value;
+ CONFIG_SYS_FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
- volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
- value = addr2[CFG_FLASH_READ0];
+ value = addr2[CONFIG_SYS_FLASH_READ0];
switch (value) {
- case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
- case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
- case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
info->flash_id = FLASH_MAN_SST;
break;
- case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
info->flash_id = FLASH_MAN_EXCEL;
break;
default:
@@ -252,104 +252,104 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
return (0); /* no or unknown flash */
}
- value = addr2[CFG_FLASH_READ1]; /* device ID */
+ value = addr2[CONFIG_SYS_FLASH_READ1]; /* device ID */
switch (value) {
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
info->flash_id += FLASH_AM320T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
info->flash_id += FLASH_AM320B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
info->flash_id += FLASH_AMDL322T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
info->flash_id += FLASH_AMDL322B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
info->flash_id += FLASH_AMDL323T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
info->flash_id += FLASH_AM640U;
info->sector_count = 128;
info->size = 0x00800000; break; /* => 8 MB */
#if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM))
- case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
info->flash_id += FLASH_SST800A;
info->sector_count = 16;
info->size = 0x00100000;
break; /* => 1 MB */
- case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A:
- case (CFG_FLASH_WORD_SIZE)SST_ID_xF1601:
- case (CFG_FLASH_WORD_SIZE)SST_ID_xF1602:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602:
info->flash_id += FLASH_SST160A;
info->sector_count = 32;
info->size = 0x00200000;
break; /* => 2 MB */
- case (CFG_FLASH_WORD_SIZE)SST_ID_xF3201:
- case (CFG_FLASH_WORD_SIZE)SST_ID_xF3202:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202:
info->flash_id += FLASH_SST320;
info->sector_count = 64;
info->size = 0x00400000;
break; /* => 4 MB */
- case (CFG_FLASH_WORD_SIZE)SST_ID_xF6401:
- case (CFG_FLASH_WORD_SIZE)SST_ID_xF6402:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401:
+ case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402:
info->flash_id += FLASH_SST640;
info->sector_count = 128;
info->size = 0x00800000;
@@ -424,19 +424,19 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
- addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+ addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
info->protect[i] = 0;
else
- info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+ info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
- *addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+ *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
}
return (info->size);
@@ -448,8 +448,8 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
- volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CFG_FLASH_WORD_SIZE *addr2;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
ulong start, now, last;
int i;
@@ -490,25 +490,25 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+ addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050; /* block erase */
for (i=0; i<50; i++)
udelay(1000); /* wait 1 ms */
} else {
if (sect == s_first) {
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+ addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
}
- addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030; /* sector erase */
}
l_sect = sect;
}
@@ -529,9 +529,9 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
start = get_timer (0);
last = start;
- addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
- while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+ while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
@@ -544,8 +544,8 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
DONE:
/* reset to read mode */
- addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
- addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
+ addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+ addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
printf (" done\n");
return 0;
@@ -630,9 +630,9 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
- volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
- volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+ volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
ulong start;
int flag;
int i;
@@ -645,11 +645,11 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
- for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
+ for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
{
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+ addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
dest2[i] = data2[i];
@@ -659,9 +659,9 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
/* data polling for D7 */
start = get_timer (0);
- while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c
index 9e2be7e..5232ddd 100644
--- a/board/esd/common/fpga.c
+++ b/board/esd/common/fpga.c
@@ -36,12 +36,12 @@
#define MAX_ONES 226
-#ifdef CFG_FPGA_PRG
-# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output) */
-# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */
-# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */
-# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */
-# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */
+#ifdef CONFIG_SYS_FPGA_PRG
+# define FPGA_PRG CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output) */
+# define FPGA_CLK CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output) */
+# define FPGA_DATA CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output) */
+# define FPGA_DONE CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input) */
+# define FPGA_INIT CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input) */
#else
# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
@@ -98,7 +98,7 @@ static int fpga_boot (const unsigned char *fpgadata, int size)
int count;
unsigned char b;
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
int j;
#else
int bit;
@@ -112,7 +112,7 @@ static int fpga_boot (const unsigned char *fpgadata, int size)
index += len + 3;
}
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
/* search for preamble 0xFFFFFFFF */
while (1) {
if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
@@ -186,7 +186,7 @@ static int fpga_boot (const unsigned char *fpgadata, int size)
DBG ("write configuration data into fpga\n");
/* write configuration-data into fpga... */
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
/*
* Load uncompressed image into fpga
*/
diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c
index c23dc81..1eea59e 100644
--- a/board/esd/common/lcd.c
+++ b/board/esd/common/lcd.c
@@ -37,7 +37,7 @@ int lcd_depth;
unsigned char *glob_lcd_reg;
unsigned char *glob_lcd_mem;
-#if defined(CFG_LCD_ENDIAN)
+#if defined(CONFIG_SYS_LCD_ENDIAN)
void lcd_setup(int lcd, int config)
{
if (lcd == 0) {
@@ -47,21 +47,21 @@ void lcd_setup(int lcd, int config)
/* set reset to low */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST);
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST);
udelay(10); /* wait 10us */
if (config == 1) {
/* big-endian */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
} else {
/* little-endian */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN);
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
}
udelay(10); /* wait 10us */
/* set reset to high */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CFG_LCD0_RST);
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST);
} else {
/*
* Set endianess and reset lcd controller 1 (big)
@@ -69,29 +69,29 @@ void lcd_setup(int lcd, int config)
/* set reset to low */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST);
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST);
udelay(10); /* wait 10us */
if (config == 1) {
/* big-endian */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
} else {
/* little-endian */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN);
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
}
udelay(10); /* wait 10us */
/* set reset to high */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CFG_LCD1_RST);
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST);
}
/*
- * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive
+ * CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
}
-#endif /* CFG_LCD_ENDIAN */
+#endif /* CONFIG_SYS_LCD_ENDIAN */
int lcd_bmp(uchar *logo_bmp)
@@ -116,20 +116,20 @@ int lcd_bmp(uchar *logo_bmp)
/*
* Decompress bmp image
*/
- len = CFG_VIDEO_LOGO_MAX_SIZE;
- dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
+ len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
+ dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
if (dst == NULL) {
printf("Error: malloc for gunzip failed!\n");
return 1;
}
- if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE,
+ if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
(uchar *)logo_bmp, &len) != 0) {
free(dst);
return 1;
}
- if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
+ if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) {
printf("Image could be truncated"
- " (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
+ " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
}
/*
diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c
index f711205..dcb764c 100644
--- a/board/esd/common/pci.c
+++ b/board/esd/common/pci.c
@@ -119,24 +119,24 @@ static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t d
/*
* Configure PLX PCI9054
*/
- pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status);
+ pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
- pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status);
+ pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
/* Check the latency timer for values >= 0x60.
*/
- pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
+ pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
if (timer < 0x60)
{
- pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
+ pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
}
/* Set I/O base register.
*/
- pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE);
- pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
+ pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
+ pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
- pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
+ pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
if (pci9054_iobase == 0xffffffff)
{
@@ -149,13 +149,13 @@ static void pci_dasa_sim_config_pci9054(struct pci_controller *hose, pci_dev_t d
static struct pci_config_table pci9054_config_table[] = {
#ifndef CONFIG_PCI_PNP
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN),
- pci_cfgfunc_config_device, { CFG_ETH_IOBASE,
- CFG_ETH_IOBASE,
+ PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
+ pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
+ CONFIG_SYS_ETH_IOBASE,
PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
#ifdef CONFIG_DASA_SIM
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN),
+ PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
pci_dasa_sim_config_pci9054 },
#endif
#endif
diff --git a/board/esd/common/xilinx_jtag/ports.h b/board/esd/common/xilinx_jtag/ports.h
index 0e38990..b702fdd 100644
--- a/board/esd/common/xilinx_jtag/ports.h
+++ b/board/esd/common/xilinx_jtag/ports.h
@@ -38,12 +38,12 @@
#define TDI (short) 2
/*
- * Use CFG_FPGA_xxx defines from board include file.
+ * Use CONFIG_SYS_FPGA_xxx defines from board include file.
*/
-#define JTAG_TMS CFG_FPGA_PRG /* output */
-#define JTAG_TCK CFG_FPGA_CLK /* output */
-#define JTAG_TDI CFG_FPGA_DATA /* output */
-#define JTAG_TDO CFG_FPGA_DONE /* input */
+#define JTAG_TMS CONFIG_SYS_FPGA_PRG /* output */
+#define JTAG_TCK CONFIG_SYS_FPGA_CLK /* output */
+#define JTAG_TDI CONFIG_SYS_FPGA_DATA /* output */
+#define JTAG_TDO CONFIG_SYS_FPGA_DONE /* input */
/* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */
void setPort(short p, short val);
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
index 54de0b8..dcab906 100644
--- a/board/esd/cpci2dp/cpci2dp.c
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -36,12 +36,12 @@ int board_early_init_f (void)
* Setup GPIO pins
*/
cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5));
+ mtdcr(cntrl0, cntrl0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
/* set output pins to high */
- out32(GPIO0_OR, CFG_EEPROM_WP);
+ out32(GPIO0_OR, CONFIG_SYS_EEPROM_WP);
/* setup for output (LED=off) */
- out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED);
+ out32(GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
@@ -67,13 +67,6 @@ int board_early_init_f (void)
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
unsigned long cntrl0Reg;
@@ -115,21 +108,7 @@ int checkboard (void)
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
* 0: disable write
@@ -139,23 +118,23 @@ phys_size_t initdram (int board_type)
* 0/1: current state if <state> was -1.
*/
int eeprom_write_enable (unsigned dev_addr, int state) {
- if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
return -1;
} else {
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+ state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
break;
}
}
@@ -163,7 +142,7 @@ int eeprom_write_enable (unsigned dev_addr, int state) {
}
#endif
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int query = argc == 1;
@@ -171,21 +150,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (query) {
/* Query write access state. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0) {
puts ("Query of write access state failed.\n");
} else {
printf ("Write access for device 0x%0x is %sabled.\n",
- CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
} else {
/* Enable write access. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
}
if (state < 0) {
puts ("Setup of write access state failed.\n");
@@ -200,4 +179,4 @@ U_BOOT_CMD(
"eepwren - Enable / disable / query EEPROM write access\n",
NULL
);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c
index de847f9..56c822e 100644
--- a/board/esd/cpci2dp/flash.c
+++ b/board/esd/cpci2dp/flash.c
@@ -47,7 +47,7 @@ unsigned long flash_init (void)
unsigned long base_b0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
diff --git a/board/esd/cpci2dp/u-boot.lds b/board/esd/cpci2dp/u-boot.lds
index 21547ac..9697cc6 100644
--- a/board/esd/cpci2dp/u-boot.lds
+++ b/board/esd/cpci2dp/u-boot.lds
@@ -72,7 +72,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -143,6 +143,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk
index 0be45c7..1bdf5e4 100644
--- a/board/esd/cpci405/config.mk
+++ b/board/esd/cpci405/config.mk
@@ -21,20 +21,4 @@
# MA 02111-1307 USA
#
-#
-# esd CPCI405 boards
-#
-
-ifeq ($(BOARD_REVISION),CPCI4052)
-TEXT_BASE = 0xFFFC0000
-else
-ifeq ($(BOARD_REVISION),CPCI405DT)
-TEXT_BASE = 0xFFFC0000
-else
-ifeq ($(BOARD_REVISION),CPCI405AB)
TEXT_BASE = 0xFFFC0000
-else
-TEXT_BASE = 0xFFFD0000
-endif
-endif
-endif
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index b856705..c5ccb34 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -110,8 +110,8 @@ int board_early_init_f (void)
* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
*/
out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
- out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
+ out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
out32(GPIO0_OR, 0); /* pull prg low */
/*
@@ -255,11 +255,6 @@ int cpci405_version(void)
}
}
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
int misc_init_r (void)
{
unsigned long cntrl0Reg;
@@ -287,8 +282,8 @@ int misc_init_r (void)
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x00300000);
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
@@ -352,13 +347,13 @@ int misc_init_r (void)
#ifdef CONFIG_CPCI405_6U
if (cpci405_version() == 3) {
- volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
- volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
+ volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
+ volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR;
/*
* Enable outputs in fpga on version 3 board
*/
- *fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
+ *fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT;
/*
* Set outputs to 0
@@ -368,9 +363,9 @@ int misc_init_r (void)
/*
* Reset external DUART
*/
- *fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
+ *fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET;
udelay(100);
- *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
+ *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET);
}
#endif
}
@@ -450,9 +445,9 @@ int checkboard (void)
#if 0 /* test-only */
if (ver >= 2) {
- volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;
+ volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1;
- if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
+ if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) {
puts ("FLASH Bank B, ");
} else {
puts ("FLASH Bank A, ");
@@ -493,18 +488,6 @@ int checkboard (void)
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
@@ -516,22 +499,20 @@ void reset_phy(void)
#endif
}
-/* ------------------------------------------------------------------------- */
-
#ifdef CONFIG_CPCI405_VER2
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
- volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
+ volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) { /* assert RESET */
- *fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
+ *fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET);
} else { /* release RESET */
- *fpga_mode |= CFG_FPGA_MODE_CF_RESET;
+ *fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET;
}
}
@@ -574,12 +555,12 @@ int pci_pre_init(struct pci_controller *hose)
#ifdef CONFIG_CPCI405AB
-#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
- |= CFG_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
- &= ~CFG_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
- & CFG_FPGA_MODE_1WIRE)
+#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
+ |= CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+#define ONE_WIRE_SET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
+ &= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+#define ONE_WIRE_GET (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \
+ & CONFIG_SYS_FPGA_MODE_1WIRE)
/*
* Generate a 1-wire reset, return 1 if no presence detect was found,
@@ -709,8 +690,8 @@ U_BOOT_CMD(
NULL
);
-#define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */
-#define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */
+#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/
/*
* Write backplane ip-address...
@@ -724,11 +705,11 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
char *ptr;
IPaddr_t ipaddr;
- buf = malloc(CFG_ENV_SIZE_2);
- if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
+ buf = malloc(CONFIG_ENV_SIZE_2);
+ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
puts("\nError reading backplane EEPROM!\n");
} else {
- crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
+ crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
if (crc != *(ulong *)buf) {
printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(ulong *)buf);
return -1;
@@ -783,14 +764,14 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
printf("Setting bp_ip to %s\n", argv[1]);
- buf = malloc(CFG_ENV_SIZE_2);
- memset(buf, 0, CFG_ENV_SIZE_2);
+ buf = malloc(CONFIG_ENV_SIZE_2);
+ memset(buf, 0, CONFIG_ENV_SIZE_2);
sprintf(str, "bp_ip=%s", argv[1]);
strcpy(buf+4, str);
- crc = crc32(0, (uchar *)(buf+4), CFG_ENV_SIZE_2-4);
+ crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
*(ulong *)buf = crc;
- if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CFG_ENV_SIZE_2)) {
+ if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
puts("\nError writing backplane EEPROM!\n");
}
diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c
index e766895..d535924 100644
--- a/board/esd/cpci405/flash.c
+++ b/board/esd/cpci405/flash.c
@@ -66,7 +66,7 @@ unsigned long flash_init (void)
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
- for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
diff --git a/board/esd/cpci405/u-boot.lds b/board/esd/cpci405/u-boot.lds
index 21547ac..5d59761 100644
--- a/board/esd/cpci405/u-boot.lds
+++ b/board/esd/cpci405/u-boot.lds
@@ -57,22 +57,7 @@ SECTIONS
.plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
@@ -143,6 +128,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c
index 20130ac..6eedb83 100644
--- a/board/esd/cpci5200/cpci5200.c
+++ b/board/esd/cpci5200/cpci5200.c
@@ -32,6 +32,7 @@
#include <mpc5xxx.h>
#include <pci.h>
#include <command.h>
+#include <netdev.h>
#include "mt46v16m16-75.h"
@@ -80,7 +81,7 @@ static void sdram_start(int hi_addr)
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
@@ -105,9 +106,9 @@ phys_size_t initdram(int board_type)
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
@@ -143,9 +144,9 @@ phys_size_t initdram(int board_type)
#if 0
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
- get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
- get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(0);
#endif
/* set SDRAM CS1 size according to the amount of RAM found */
@@ -179,10 +180,10 @@ void flash_afterinit(ulong size)
/* adjust mapping */
*(vu_long *) MPC5XXX_BOOTCS_START =
*(vu_long *) MPC5XXX_CS0_START =
- START_REG(CFG_BOOTCS_START | size);
+ START_REG(CONFIG_SYS_BOOTCS_START | size);
*(vu_long *) MPC5XXX_BOOTCS_STOP =
*(vu_long *) MPC5XXX_CS0_STOP =
- STOP_REG(CFG_BOOTCS_START | size, size);
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
}
}
@@ -259,6 +260,11 @@ void init_ata_reset(void)
}
}
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
unsigned int addr;
diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c
index d76af02..9b578b5 100644
--- a/board/esd/cpci5200/strataflash.c
+++ b/board/esd/cpci5200/strataflash.c
@@ -102,7 +102,7 @@ typedef union {
#define NUM_ERASE_REGIONS 4
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
@@ -121,7 +121,7 @@ static int flash_write_cfiword(flash_info_t * info, ulong dest,
cfiword_t cword);
static int flash_full_status_check(flash_info_t * info, ulong sector,
ulong tout, char *prompt);
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
int len);
#endif
@@ -185,14 +185,14 @@ unsigned long flash_init(void)
*
*/
- address = CFG_FLASH_BASE;
+ address = CONFIG_SYS_FLASH_BASE;
size = 0;
/* Init: no FLASHes known */
- for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
size += flash_info[i].size = flash_get_size(address, i);
- address += CFG_FLASH_INCREMENT;
+ address += CONFIG_SYS_FLASH_INCREMENT;
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf
("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
@@ -202,9 +202,9 @@ unsigned long flash_init(void)
#if 0 /* test-only */
/* Monitor protection ON by default */
-#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
for (i = 0;
- flash_info[0].start[i] < CFG_MONITOR_BASE + monitor_flash_len - 1;
+ flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1;
i++)
(void)flash_real_protect(&flash_info[0], i, 1);
#endif
@@ -326,7 +326,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
return rc;
wp = cp;
}
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
while (cnt >= info->portwidth) {
i = info->buffer_size > cnt ? cnt : info->buffer_size;
if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
@@ -347,7 +347,7 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
wp += info->portwidth;
cnt -= info->portwidth;
}
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
if (cnt == 0) {
return (0);
}
@@ -727,7 +727,7 @@ static int flash_write_cfiword(flash_info_t * info, ulong dest, cfiword_t cword)
return flash_full_status_check(info, 0, info->write_tout, "write");
}
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
/* loop through the sectors from the highest address
* when the passed address is greater or equal to the sector address
@@ -801,4 +801,4 @@ static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
return retcode;
}
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 5ab76c6..70bae60 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -125,7 +125,7 @@ extern flash_info_t flash_info[];
/* ------------------------------------------------------------------------- */
/* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
/* Unfortunately, we cant change it while we are in flash, so we initialize it
* to the "final" value. This means that any debug_led calls before
@@ -134,7 +134,7 @@ extern flash_info_t flash_info[];
*/
void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
int display_mem_map (void);
/* ------------------------------------------------------------------------- */
@@ -197,7 +197,7 @@ static void gt_pci_config (void)
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CFG_PCI_IDSEL);
+ (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
@@ -206,7 +206,7 @@ static void gt_pci_config (void)
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
- (stat & 0xffff0000) | CFG_PCI_IDSEL);
+ (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
}
/* Enable master */
@@ -224,21 +224,21 @@ static void gt_pci_config (void)
/* ronen- add write to pci remap registers for 64460.
in 64360 when writing to pci base go and overide remap automaticaly,
in 64460 it doesn't */
- GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
+ GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
+ GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
- GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
- GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
+ GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
+ GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
- GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+ GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+ GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
/* PCI interface settings */
/* Timeout set to retry forever */
@@ -254,7 +254,7 @@ static void gt_pci_config (void)
for (stat = 0; stat <= PCI_HOST1; stat++)
pciWriteConfigReg (stat,
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
- SELF, CFG_GT_REGS);
+ SELF, CONFIG_SYS_GT_REGS);
#endif
}
@@ -270,7 +270,7 @@ static void gt_cpu_config (void)
tmp = GTREGREAD (CPU_CONFIGURATION);
/* set the SINGLE_CPU bit see MV64360 P.399 */
-#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
tmp |= CPU_CONF_SINGLE_CPU;
#endif
@@ -320,7 +320,7 @@ int board_early_init_f (void)
* it last time. (huber)
*/
- my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+ my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
/* No PCI in first release of Port To_do: enable it. */
#ifdef CONFIG_PCI
@@ -364,45 +364,45 @@ int board_early_init_f (void)
* registers to boot from the sram. (device0)
*/
- memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
- memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
- memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
- memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+ memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+ memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+ memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+ memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
/* configure device timing */
- GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
- GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
- GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_DEV3_PAR);
+ GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
+ GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
+ GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
+ GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
-#ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
/* detect if we are booting from the 32 bit flash */
if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
/* 32 bit boot flash */
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+ GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
- CFG_32BIT_BOOT_PAR);
+ CONFIG_SYS_32BIT_BOOT_PAR);
} else {
/* 8 bit boot flash */
- GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
- GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+ GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+ GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
}
#else
/* 8 bit boot flash only */
-/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+/* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
#endif
gt_cpu_config ();
/* MPP setup */
- GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
- GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
- GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
- GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+ GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+ GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+ GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+ GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
- GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+ GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
DEBUG_LED0_ON ();
DEBUG_LED1_ON ();
DEBUG_LED2_ON ();
@@ -415,7 +415,7 @@ int board_early_init_f (void)
int misc_init_r ()
{
icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
l2cache_enable ();
#endif
#ifdef CONFIG_MPSC
@@ -428,19 +428,19 @@ int misc_init_r ()
/* disable the dcache and MMU */
dcache_lock ();
#endif
- if (flash_info[3].size < CFG_FLASH_INCREMENT) {
+ if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
unsigned int flash_offset;
unsigned int l;
- flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size;
- for (l = 0; l < CFG_MAX_FLASH_SECT; l++) {
+ flash_offset = CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
+ for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
if (flash_info[3].start[l] != 0) {
flash_info[3].start[l] += flash_offset;
}
}
flash_protect (FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + monitor_flash_len - 1,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[3]);
}
return 0;
@@ -449,7 +449,7 @@ int misc_init_r ()
void after_reloc (ulong dest_addr, gd_t * gd)
{
- memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
+ memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
display_mem_map ();
/* now, jump to the main ppcboot board init code */
@@ -469,7 +469,7 @@ int checkboard (void)
{
int l_type = 0;
- printf ("BOARD: %s\n", CFG_BOARD_NAME);
+ printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
return (l_type);
}
@@ -540,7 +540,7 @@ int display_mem_map (void)
/* DRAM check routines copied from gw8260 */
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
/*********************************************************************/
/* NAME: move64() - moves a double word (64-bit) */
@@ -571,7 +571,7 @@ static void move64 (unsigned long long *src, unsigned long long *dest)
}
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
unsigned long long pattern[] = {
0xaaaaaaaaaaaaaaaaLL,
@@ -634,7 +634,7 @@ unsigned long long pattern[] = {
/*********************************************************************/
int mem_test_data (void)
{
- unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+ unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
unsigned long long temp64 = 0;
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
@@ -661,9 +661,9 @@ int mem_test_data (void)
return 0;
}
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
/*********************************************************************/
/* NAME: mem_test_address() - test address lines */
/* */
@@ -688,8 +688,8 @@ int mem_test_data (void)
int mem_test_address (void)
{
volatile unsigned int *pmem =
- (volatile unsigned int *) CFG_MEMTEST_START;
- const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+ (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+ const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
unsigned int i;
/* write address to each location */
@@ -706,9 +706,9 @@ int mem_test_address (void)
}
return 0;
}
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
/*********************************************************************/
/* NAME: mem_march() - memory march */
/* */
@@ -766,7 +766,7 @@ int mem_march (volatile unsigned long long *base,
}
return 0;
}
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
/*********************************************************************/
/* NAME: mem_test_walk() - a simple walking ones test */
@@ -798,8 +798,8 @@ int mem_test_walk (void)
{
unsigned long long mask;
volatile unsigned long long *pmem =
- (volatile unsigned long long *) CFG_MEMTEST_START;
- const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+ (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+ const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
unsigned int i;
@@ -865,23 +865,23 @@ int testdram (void)
int runaddress = 0;
int runwalk = 0;
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
s = getenv ("testdramdata");
rundata = (s && (*s == 'y')) ? 1 : 0;
#endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
s = getenv ("testdramaddress");
runaddress = (s && (*s == 'y')) ? 1 : 0;
#endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
s = getenv ("testdramwalk");
runwalk = (s && (*s == 'y')) ? 1 : 0;
#endif
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
- printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+ printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
}
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
if (rundata == 1) {
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
@@ -891,7 +891,7 @@ int testdram (void)
printf ("ok \n");
}
#endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
@@ -901,7 +901,7 @@ int testdram (void)
printf ("ok \n");
}
#endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
if (runwalk == 1) {
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
@@ -917,7 +917,7 @@ int testdram (void)
return 0;
}
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
/* ronen - the below functions are used by the bootm function */
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
@@ -956,7 +956,7 @@ void board_prebootm_init ()
/* GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
/* Relocate MV64360 internal regs */
- my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS);
+ my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
icache_disable ();
dcache_disable ();
diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c
index 5b1bc01..d95567f 100644
--- a/board/esd/cpci750/i2c.c
+++ b/board/esd/cpci750/i2c.c
@@ -46,7 +46,7 @@ static void i2c_init (int speed, int slaveaddr)
unsigned int n, m, freq, margin, power;
unsigned int actualN = 0, actualM = 0;
unsigned int minMargin = 0xffffffff;
- unsigned int tclk = CFG_TCLK;
+ unsigned int tclk = CONFIG_SYS_TCLK;
unsigned int i2cFreq = speed; /* 100000 max. Fast mode not supported */
DP (puts ("i2c_init\n"));
@@ -380,7 +380,7 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data,
int len)
{
uchar status = 0;
- unsigned int i2cFreq = CFG_I2C_SPEED;
+ unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_read\n"));
@@ -428,7 +428,7 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data,
int len)
{
uchar status = 0;
- unsigned int i2cFreq = CFG_I2C_SPEED;
+ unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_write\n"));
@@ -464,7 +464,7 @@ int i2c_probe (uchar chip)
unsigned int i2c_status;
#endif
uchar status = 0;
- unsigned int i2cFreq = CFG_I2C_SPEED;
+ unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
DP (puts ("i2c_probe\n"));
diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c
index 0adafe2..9bdc523 100644
--- a/board/esd/cpci750/ide.c
+++ b/board/esd/cpci750/ide.c
@@ -30,7 +30,7 @@
#include <ide.h>
#include <pci.h>
-extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
+extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
int ide_preinit (void)
{
@@ -39,7 +39,7 @@ int ide_preinit (void)
int l;
status = 1;
- for (l = 0; l < CFG_IDE_MAXBUS; l++) {
+ for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
ide_bus_offset[l] = -ATA_STATUS;
}
devbusfn = pci_find_device (0x1103, 0x0004, 0);
@@ -51,11 +51,11 @@ int ide_preinit (void)
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
(u32 *) & ide_bus_offset[0]);
ide_bus_offset[0] &= 0xfffffffe;
- ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
+ ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
(u32 *) & ide_bus_offset[1]);
ide_bus_offset[1] &= 0xfffffffe;
- ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
+ ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
}
return (status);
}
diff --git a/board/esd/cpci750/local.h b/board/esd/cpci750/local.h
index bca0e1f..de3758a 100644
--- a/board/esd/cpci750/local.h
+++ b/board/esd/cpci750/local.h
@@ -48,7 +48,7 @@
/* #define CONFIG_BOOTCOMMAND */
/* #define CONFIG_RAMBOOTCOMMAND */
/* #define CONFIG_NFSBOOTCOMMAND */
-/* #define CFG_AUTOLOAD */
+/* #define CONFIG_SYS_AUTOLOAD */
/* #define CONFIG_PREBOOT */
/* These don't */
diff --git a/board/esd/cpci750/misc.S b/board/esd/cpci750/misc.S
index 160b1d3..233fd83 100644
--- a/board/esd/cpci750/misc.S
+++ b/board/esd/cpci750/misc.S
@@ -16,7 +16,7 @@
board_relocate_rom:
mflr r7
/* update the location of the GT registers */
- lis r11, CFG_GT_REGS@h
+ lis r11, CONFIG_SYS_GT_REGS@h
/* if we're using ECC, we must use the DMA engine to copy ourselves */
bl start_idma_transfer_0
bl wait_for_idma_0
@@ -29,12 +29,12 @@ board_relocate_rom:
board_init_ecc:
mflr r7
/* NOTE: r10 still contains the location we've been relocated to
- * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+ * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
/* now that we're running from ram, init the rest of main memory
* for ECC use */
- lis r8, CFG_MONITOR_LEN@h
- ori r8, r8, CFG_MONITOR_LEN@l
+ lis r8, CONFIG_SYS_MONITOR_LEN@h
+ ori r8, r8, CONFIG_SYS_MONITOR_LEN@l
divw r3, r10, r8
@@ -120,15 +120,15 @@ stop_idma_engine_0:
blr
#endif
-#ifdef CFG_BOARD_ASM_INIT
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
/* NOTE: trashes r3-r7 */
.globl board_asm_init
board_asm_init:
/* just move the GT registers to where they belong */
- lis r3, CFG_DFL_GT_REGS@h
- ori r3, r3, CFG_DFL_GT_REGS@l
- lis r4, CFG_GT_REGS@h
- ori r4, r4, CFG_GT_REGS@l
+ lis r3, CONFIG_SYS_DFL_GT_REGS@h
+ ori r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+ lis r4, CONFIG_SYS_GT_REGS@h
+ ori r4, r4, CONFIG_SYS_GT_REGS@l
li r5, INTERNAL_SPACE_DECODE
/* test to see if we've already moved */
@@ -153,11 +153,11 @@ board_asm_init:
cmp cr0, r7, r6
bne 1b
- lis r3, CFG_INT_SRAM_BASE@h
- ori r3, r3, CFG_INT_SRAM_BASE@l
+ lis r3, CONFIG_SYS_INT_SRAM_BASE@h
+ ori r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
rlwinm r3, r3, 16, 16, 31
- lis r4, CFG_GT_REGS@h
- ori r4, r4, CFG_GT_REGS@l
+ lis r4, CONFIG_SYS_GT_REGS@h
+ ori r4, r4, CONFIG_SYS_GT_REGS@l
li r5, INTEGRATED_SRAM_BASE_ADDR
stwbrx r3, r5, r4
diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c
index fa8d3bd..c89426d 100644
--- a/board/esd/cpci750/mpsc.c
+++ b/board/esd/cpci750/mpsc.c
@@ -427,7 +427,7 @@ void mpsc_sdma_init (void)
(MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
/* Setup MPSC internal address space base address */
- GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+ GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
/* no high address remap*/
GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -517,9 +517,9 @@ int galbrg_set_baudrate (int channel, int rate)
#ifdef ZUMA_NTL
/* from tclk */
- clock = (CFG_TCLK / (16 * rate)) - 1;
+ clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
#else
- clock = (CFG_TCLK / (16 * rate)) - 1;
+ clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
#endif
galbrg_set_CDV (channel, clock); /* set timer Reg. for BRG */
diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c
index c335ebf..bfc7e55 100644
--- a/board/esd/cpci750/pci.c
+++ b/board/esd/cpci750/pci.c
@@ -66,13 +66,13 @@ static void gt_pci_bus_mode_display (PCI_HOST host)
printf ("PCI %d bus mode: Conventional PCI\n", host);
break;
case 1:
- printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
+ printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
break;
case 2:
- printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
+ printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
break;
case 3:
- printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
+ printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
break;
default:
printf ("Unknown BUS %d\n", mode);
@@ -932,14 +932,14 @@ void pci_init_board (void)
/* PCI memory space */
pci_set_region (pci0_hose.regions + 0,
- CFG_PCI0_0_MEM_SPACE,
- CFG_PCI0_0_MEM_SPACE,
- CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+ CONFIG_SYS_PCI0_0_MEM_SPACE,
+ CONFIG_SYS_PCI0_0_MEM_SPACE,
+ CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci0_hose.regions + 1,
- CFG_PCI0_IO_SPACE_PCI,
- CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+ CONFIG_SYS_PCI0_IO_SPACE_PCI,
+ CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci0_hose,
pci_hose_read_config_byte_via_dword,
@@ -981,14 +981,14 @@ void pci_init_board (void)
/* PCI memory space */
pci_set_region (pci1_hose.regions + 0,
- CFG_PCI1_0_MEM_SPACE,
- CFG_PCI1_0_MEM_SPACE,
- CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+ CONFIG_SYS_PCI1_0_MEM_SPACE,
+ CONFIG_SYS_PCI1_0_MEM_SPACE,
+ CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (pci1_hose.regions + 1,
- CFG_PCI1_IO_SPACE_PCI,
- CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+ CONFIG_SYS_PCI1_IO_SPACE_PCI,
+ CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
pci_set_ops (&pci1_hose,
pci_hose_read_config_byte_via_dword,
diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c
index 0291937..4c03630 100644
--- a/board/esd/cpci750/sdram_init.c
+++ b/board/esd/cpci750/sdram_init.c
@@ -350,7 +350,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
} else
dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
-#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
for (i = 0; i <= 127; i++) {
printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
@@ -1656,13 +1656,13 @@ initdram(int board_type)
if (dimmInfo2.numOfModuleBanks > 2)
printf("Error, SPD claims DIMM2 has >2 banks\n");
- for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+ for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
/* skip over banks that are not populated */
if (! checkbank[bank_no])
continue;
- if ((total + check) > CFG_GT_REGS)
- check = CFG_GT_REGS - total;
+ if ((total + check) > CONFIG_SYS_GT_REGS)
+ check = CONFIG_SYS_GT_REGS - total;
memory_map_bank(bank_no, total, check);
realsize = dram_size((long int *)total, check);
diff --git a/board/esd/cpci750/u-boot.lds b/board/esd/cpci750/u-boot.lds
index 1a95755..ff2d8b7 100644
--- a/board/esd/cpci750/u-boot.lds
+++ b/board/esd/cpci750/u-boot.lds
@@ -60,7 +60,7 @@ SECTIONS
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
-/* common/environment.o(.text) */
+/* common/env_embedded.o(.text) */
*(.text)
*(.fixup)
@@ -131,6 +131,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c
index 204117e..b5d2543 100644
--- a/board/esd/cpciiser4/cpciiser4.c
+++ b/board/esd/cpciiser4/cpciiser4.c
@@ -183,22 +183,3 @@ int checkboard (void)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- return (16 * 1024 * 1024);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c
index de847f9..56c822e 100644
--- a/board/esd/cpciiser4/flash.c
+++ b/board/esd/cpciiser4/flash.c
@@ -47,7 +47,7 @@ unsigned long flash_init (void)
unsigned long base_b0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
diff --git a/board/esd/cpciiser4/u-boot.lds b/board/esd/cpciiser4/u-boot.lds
index 21547ac..9697cc6 100644
--- a/board/esd/cpciiser4/u-boot.lds
+++ b/board/esd/cpciiser4/u-boot.lds
@@ -72,7 +72,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -143,6 +143,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c
index 89a4aaf..36dd58c 100644
--- a/board/esd/dasa_sim/cmd_dasa_sim.c
+++ b/board/esd/dasa_sim/cmd_dasa_sim.c
@@ -48,13 +48,13 @@ static unsigned int PciEepromReadLongVPD (int offs)
unsigned int ret;
int count;
- pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c,
+ pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
(offs << 16) | 0x0003);
count = 0;
for (;;) {
udelay (10 * 1000);
- pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret);
+ pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
if ((ret & 0x80000000) != 0) {
break;
} else {
@@ -66,7 +66,7 @@ static unsigned int PciEepromReadLongVPD (int offs)
}
}
- pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x50, &value);
+ pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value);
return value;
}
@@ -77,14 +77,14 @@ static int PciEepromWriteLongVPD (int offs, unsigned int value)
unsigned int ret;
int count;
- pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x50, value);
- pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c,
+ pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value);
+ pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
(offs << 16) | 0x80000003);
count = 0;
for (;;) {
udelay (10 * 1000);
- pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret);
+ pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
if ((ret & 0x80000000) == 0) {
break;
} else {
@@ -109,7 +109,7 @@ static void showPci9054 (void)
for (l = 0; l < 6; l++) {
printf ("%02x: ", l * 0x10);
for (i = 0; i < 4; i++) {
- pci_read_config_dword (CFG_PCI9054_DEV_FN,
+ pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN,
l * 16 + i * 4,
(unsigned int *)&val);
printf ("%08x ", val);
diff --git a/board/esd/dasa_sim/dasa_sim.c b/board/esd/dasa_sim/dasa_sim.c
index fb0c77e..47d6bb3 100644
--- a/board/esd/dasa_sim/dasa_sim.c
+++ b/board/esd/dasa_sim/dasa_sim.c
@@ -22,6 +22,7 @@
*/
#include <common.h>
+#include <netdev.h>
#include "dasa_sim.h"
/* ------------------------------------------------------------------------- */
@@ -203,22 +204,7 @@ int checkboard (void)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/esd/dasa_sim/flash.c b/board/esd/dasa_sim/flash.c
index d2ac13f..9c71b04 100644
--- a/board/esd/dasa_sim/flash.c
+++ b/board/esd/dasa_sim/flash.c
@@ -47,7 +47,7 @@ unsigned long flash_init (void)
unsigned long base_b0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds
index 67d72f7..6acf7b8 100644
--- a/board/esd/dasa_sim/u-boot.lds
+++ b/board/esd/dasa_sim/u-boot.lds
@@ -78,7 +78,6 @@ SECTIONS
common/cmd_mem.o (.text)
common/cmd_nvedit.o (.text)
common/console.o (.text)
- common/lists.o (.text)
common/main.o (.text)
board/esd/dasa_sim/flash.o (.text)
@@ -87,7 +86,7 @@ SECTIONS
net/bootp.o (.text)
. = env_offset;
- common/environment.o(.text)
+ common/env_embedded.o(.text)
*(.text)
*(.fixup)
@@ -158,6 +157,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c
index bb3baa4..eb001da 100644
--- a/board/esd/dp405/dp405.c
+++ b/board/esd/dp405/dp405.c
@@ -74,15 +74,6 @@ int board_early_init_f (void)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
/* adjust flash start and offset */
@@ -119,30 +110,3 @@ int checkboard (void)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/dp405/flash.c
+++ b/board/esd/dp405/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -91,7 +91,7 @@ unsigned long flash_init (void)
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
diff --git a/board/esd/dp405/u-boot.lds b/board/esd/dp405/u-boot.lds
index d70d379..d8fbea3 100644
--- a/board/esd/dp405/u-boot.lds
+++ b/board/esd/dp405/u-boot.lds
@@ -66,14 +66,14 @@ SECTIONS
cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/4xx_enet.o (.text)
+ drivers/net/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -144,6 +144,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
index 78ae4ba..8a87d55 100644
--- a/board/esd/du405/du405.c
+++ b/board/esd/du405/du405.c
@@ -198,18 +198,3 @@ int checkboard (void)
return 0;
}
-
-
-phys_size_t initdram (int board_type)
-{
- return (16 * 1024 * 1024);
-}
-
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c
index 14549c0..240aa09 100644
--- a/board/esd/du405/flash.c
+++ b/board/esd/du405/flash.c
@@ -47,7 +47,7 @@ unsigned long flash_init (void)
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
- for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
diff --git a/board/esd/du405/u-boot.lds b/board/esd/du405/u-boot.lds
index 46ef7e7..858ae61 100644
--- a/board/esd/du405/u-boot.lds
+++ b/board/esd/du405/u-boot.lds
@@ -72,7 +72,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -143,6 +143,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/du440/config.mk b/board/esd/du440/config.mk
index 5164334..91e65ec 100644
--- a/board/esd/du440/config.mk
+++ b/board/esd/du440/config.mk
@@ -33,5 +33,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 8765cc1..2f97a12 100644
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -29,7 +29,7 @@
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
extern ulong flash_get_size (ulong base, int banknum);
int usbhub_init(void);
@@ -51,31 +51,31 @@ int board_early_init_f(void)
/*
* Setup the GPIO pins
*/
- out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP);
- out_be32((void*)GPIO0_TCR, 0x0000000f | CFG_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
+ out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
out_be32((void*)GPIO0_OSRL, 0x50055400);
- out_be32((void*)GPIO0_OSRH, 0x550050aa);
+ out_be32((void*)GPIO0_OSRH, 0x55005000);
out_be32((void*)GPIO0_TSRL, 0x50055400);
out_be32((void*)GPIO0_TSRH, 0x55005000);
out_be32((void*)GPIO0_ISR1L, 0x50000000);
out_be32((void*)GPIO0_ISR1H, 0x00000000);
out_be32((void*)GPIO0_ISR2L, 0x00000000);
- out_be32((void*)GPIO0_ISR2H, 0x00000100);
+ out_be32((void*)GPIO0_ISR2H, 0x00000000);
out_be32((void*)GPIO0_ISR3L, 0x00000000);
out_be32((void*)GPIO0_ISR3H, 0x00000000);
out_be32((void*)GPIO1_OR, 0x00000000);
out_be32((void*)GPIO1_TCR, 0xc2000000 |
- CFG_GPIO1_IORSTN |
- CFG_GPIO1_IORST2N |
- CFG_GPIO1_LEDUSR1 |
- CFG_GPIO1_LEDUSR2 |
- CFG_GPIO1_LEDPOST |
- CFG_GPIO1_LEDDU);
- out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
- out_be32((void*)GPIO1_OSRL, 0x5c280000);
+ CONFIG_SYS_GPIO1_IORSTN |
+ CONFIG_SYS_GPIO1_IORST2N |
+ CONFIG_SYS_GPIO1_LEDUSR1 |
+ CONFIG_SYS_GPIO1_LEDUSR2 |
+ CONFIG_SYS_GPIO1_LEDPOST |
+ CONFIG_SYS_GPIO1_LEDDU);
+ out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
+ out_be32((void*)GPIO1_OSRL, 0x0c280000);
out_be32((void*)GPIO1_OSRH, 0x00000000);
- out_be32((void*)GPIO1_TSRL, 0x0c000000);
+ out_be32((void*)GPIO1_TSRL, 0xcc000000);
out_be32((void*)GPIO1_TSRH, 0x00000000);
out_be32((void*)GPIO1_ISR1L, 0x00005550);
out_be32((void*)GPIO1_ISR1H, 0x00000000);
@@ -154,8 +154,8 @@ int board_early_init_f(void)
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
- (0x80000000 >> (28 + CFG_NAND0_CS)) |
- (0x80000000 >> (28 + CFG_NAND1_CS));
+ (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
+ (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
return 0;
@@ -169,6 +169,7 @@ int misc_init_r(void)
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1;
+ unsigned long sdr0_srst0, sdr0_srst1;
int i, j;
/* adjust flash start and offset */
@@ -223,10 +224,38 @@ int misc_init_r(void)
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
- /* clear resets */
- udelay (1000);
+ /*
+ * Take USB out of reset:
+ * -Initial status = all cores are in reset
+ * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
+ * -wait 1 ms
+ * -deassert reset to PHY
+ * -wait 1 ms
+ * -deassert reset to HOST
+ * -wait 4 ms
+ * -deassert all other resets
+ */
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
+ SDR0_SRST1_P4OPB0 | \
+ SDR0_SRST1_OPBA2 | \
+ SDR0_SRST1_PLB42OPB1 | \
+ SDR0_SRST1_OPB2PLB40);
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+ udelay(1000);
+
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+ udelay(1000);
+
+ mfsdr(SDR0_SRST0, sdr0_srst0);
+ sdr0_srst0 &= ~SDR0_SRST0_USB2H;
+ mtsdr(SDR0_SRST0, sdr0_srst0);
+ udelay(4000);
+
+ /* finally all the other resets */
mtsdr(SDR0_SRST1, 0x00000000);
- udelay (1000);
mtsdr(SDR0_SRST0, 0x00000000);
printf("USB: Host(int phy)\n");
@@ -244,7 +273,7 @@ int misc_init_r(void)
* We have to wait at least 560ms until we may call usbhub_init
*/
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
- CFG_GPIO1_IORSTN | CFG_GPIO1_IORST2N);
+ CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
/*
* flash USR1/2 LEDs (600ms)
@@ -253,22 +282,22 @@ int misc_init_r(void)
*/
for (j = 0; j < 3; j++) {
out_be32((void*)GPIO1_OR,
- (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR2) |
- CFG_GPIO1_LEDUSR1);
+ (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
+ CONFIG_SYS_GPIO1_LEDUSR1);
for (i = 0; i < 100; i++)
udelay(1000);
out_be32((void*)GPIO1_OR,
- (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR1) |
- CFG_GPIO1_LEDUSR2);
+ (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
+ CONFIG_SYS_GPIO1_LEDUSR2);
for (i = 0; i < 100; i++)
udelay(1000);
}
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
- ~(CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2));
+ ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
if (usbhub_init())
du440_post_errors++;
@@ -281,14 +310,14 @@ int misc_init_r(void)
int pld_revision(void)
{
- out8(CFG_CPLD_BASE, 0x00);
- return (int)(in8(CFG_CPLD_BASE) & CPLD_VERSION_MASK);
+ out8(CONFIG_SYS_CPLD_BASE, 0x00);
+ return (int)(in8(CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
}
int board_revision(void)
{
- int rpins = (int)((in_be32((void*)GPIO1_IR) & CFG_GPIO1_HWVER_MASK)
- >> CFG_GPIO1_HWVER_SHIFT);
+ int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
+ >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
((rpins & 4) >> 1) | ((rpins & 8) >> 3);
@@ -299,7 +328,7 @@ void board_show_activity (ulong timestamp)
{
if ((timestamp % 100) == 0)
out_be32((void*)GPIO1_OR,
- in_be32((void*)GPIO1_OR) ^ CFG_GPIO1_LEDUSR1);
+ in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
}
void show_activity(int arg)
@@ -392,7 +421,7 @@ int pci_pre_init(struct pci_controller *hose)
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*
@@ -408,16 +437,16 @@ void pci_target_init(struct pci_controller *hose)
*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+ out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
/* and enable region */
@@ -450,9 +479,9 @@ void pci_target_init(struct pci_controller *hose)
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
@@ -467,7 +496,7 @@ void pci_master_init(struct pci_controller *hose)
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
/*
* is_pci_host
@@ -495,18 +524,18 @@ int last_stage_init(void)
int e, i;
/* everyting is ok: turn on POST-LED */
- out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
/* slowly blink on errors and finally keep LED off */
for (e = 0; e < du440_post_errors; e++) {
out_be32((void*)GPIO1_OR,
- in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+ in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
for (i = 0; i < 500; i++)
udelay(1000);
out_be32((void*)GPIO1_OR,
- in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDPOST);
+ in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
for (i = 0; i < 500; i++)
udelay(1000);
@@ -554,9 +583,9 @@ int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf("ERROR - no signal\n");
t1 = t2 = 0;
- pinold = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+ pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
while (!ctrlc()) {
- pin = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+ pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
if (pin && !pinold) { /* bit start */
t1 = get_ticks();
if (t2 && ((unsigned int)(t1 - t2) /
@@ -632,7 +661,7 @@ U_BOOT_CMD(
);
#endif /* CONFIG_I2C_MULTI_BUS */
-#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
int boot_eeprom_write (unsigned dev_addr,
unsigned offset,
uchar *buffer,
@@ -642,7 +671,7 @@ int boot_eeprom_write (unsigned dev_addr,
unsigned blk_off;
int rcode = 0;
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
eeprom_write_enable(dev_addr, 1);
#endif
/*
@@ -671,9 +700,9 @@ int boot_eeprom_write (unsigned dev_addr,
* bytes that can be ccessed with the single read or write
* operation.
*/
-#if defined(CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
-#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
maxlen = BOOT_EEPROM_PAGE_SIZE -
@@ -693,11 +722,11 @@ int boot_eeprom_write (unsigned dev_addr,
buffer += len;
offset += len;
-#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
- udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
}
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
eeprom_write_enable(dev_addr, 0);
#endif
return rcode;
@@ -733,6 +762,12 @@ int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* sdsdp[1]=0x095fa030; */
sdsdp[2] = 0x40082350;
sdsdp[3] = 0x0d050000;
+ } else if (!strcmp(argv[1], "667-166")) {
+ printf("Bootstrapping for 667-166MHz\n");
+ sdsdp[0] = 0x8778a252;
+ sdsdp[1] = 0x09d7a030;
+ sdsdp[2] = 0x40082350;
+ sdsdp[3] = 0x0d050000;
}
} else {
printf("Bootstrapping for 533MHz (default)\n");
@@ -744,7 +779,7 @@ int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
printf("Writing boot EEPROM ...\n");
- if (boot_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
+ if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
0, (uchar*)sdsdp, 16) != 0)
printf("boot_eeprom_write failed\n");
else
@@ -758,7 +793,7 @@ U_BOOT_CMD(
NULL
);
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
/*
* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
@@ -770,27 +805,27 @@ U_BOOT_CMD(
*/
int eeprom_write_enable (unsigned dev_addr, int state)
{
- if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
- (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr))
+ if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
+ (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
return -1;
else {
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) & ~CFG_GPIO0_EP_EEP);
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
out_be32((void*)GPIO0_OR,
- in_be32((void*)GPIO0_OR) | CFG_GPIO0_EP_EEP);
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
state = 0;
break;
default:
/* Read current status back. */
state = (0 == (in_be32((void*)GPIO0_OR) &
- CFG_GPIO0_EP_EEP));
+ CONFIG_SYS_GPIO0_EP_EEP));
break;
}
}
@@ -804,21 +839,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (query) {
/* Query write access state. */
- state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0)
puts ("Query of write access state failed.\n");
else {
printf ("Write access for device 0x%0x is %sabled.\n",
- CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
- state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
} else {
/* Enable write access. */
- state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
}
if (state < 0)
puts ("Setup of write access state failed.\n");
@@ -830,19 +865,19 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
"eepwren - Enable / disable / query EEPROM write access\n",
NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
static int got_pldirq;
static int pld_interrupt(u32 arg)
{
int rc = -1; /* not for us */
- u8 status = in8(CFG_CPLD_BASE);
+ u8 status = in8(CONFIG_SYS_CPLD_BASE);
/* check for PLD interrupt */
if (status & PWR_INT_FLAG) {
/* reset this int */
- out8(CFG_CPLD_BASE, 0);
+ out8(CONFIG_SYS_CPLD_BASE, 0);
rc = 0;
got_pldirq = 1; /* trigger backend */
}
@@ -855,7 +890,7 @@ int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
got_pldirq = 0;
/* clear any pending interrupt */
- out8(CFG_CPLD_BASE, 0);
+ out8(CONFIG_SYS_CPLD_BASE, 0);
irq_install_handler(CPLD_IRQ,
(interrupt_handler_t *)pld_interrupt, 0);
@@ -871,7 +906,7 @@ int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (got_pldirq) {
printf("Got interrupt!\n");
printf("Power %sready!\n",
- in8(CFG_CPLD_BASE) & PWR_RDY ? "":"NOT ");
+ in8(CONFIG_SYS_CPLD_BASE) & PWR_RDY ? "":"NOT ");
}
irq_free_handler(CPLD_IRQ);
@@ -935,7 +970,7 @@ U_BOOT_CMD(
int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned long long start, end;
- char c, cmd[CFG_CBSIZE];
+ char c, cmd[CONFIG_SYS_CBSIZE];
char *p, *d = cmd;
int ret, i;
ulong us;
@@ -963,7 +998,7 @@ int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return ret;
}
U_BOOT_CMD(
- time, CFG_MAXARGS, 1, do_time,
+ time, CONFIG_SYS_MAXARGS, 1, do_time,
"time - run command and output execution time\n",
NULL
);
@@ -1013,7 +1048,7 @@ int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
}
U_BOOT_CMD(
- gfxdemo, CFG_MAXARGS, 1, do_gfxdemo,
+ gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,
"gfxdemo - demo\n",
NULL
);
diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h
index 83fdac7..a124a7e 100644
--- a/board/esd/du440/du440.h
+++ b/board/esd/du440/du440.h
@@ -20,18 +20,18 @@
#define SDR0_USB0 0x0320 /* USB Control Register */
-#define CFG_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
-#define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
+#define CONFIG_SYS_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
+#define CONFIG_SYS_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
-#define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
-#define CFG_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */
+#define CONFIG_SYS_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
+#define CONFIG_SYS_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */
-#define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
-#define CFG_GPIO1_HWVER_SHIFT 4
-#define CFG_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
-#define CFG_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
-#define CFG_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
-#define CFG_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
+#define CONFIG_SYS_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
+#define CONFIG_SYS_GPIO1_HWVER_SHIFT 4
+#define CONFIG_SYS_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
+#define CONFIG_SYS_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
+#define CONFIG_SYS_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
+#define CONFIG_SYS_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
#define CPLD_VERSION_MASK 0x0f
#define PWR_INT_FLAG 0x80
diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
index 4390b50..3cac6b1 100644
--- a/board/esd/du440/init.S
+++ b/board/esd/du440/init.S
@@ -44,30 +44,30 @@ tlbtab:
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
#endif
/* TLB-entry for PCI Memory */
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
/* TLB-entry for PCI IO */
- tlbentry( CFG_PCI_IOBASE, SZ_64K, CFG_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
/* TLB-entries for EBC: CPLD, DUMEM, DUIO */
- tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_DUMEM_BASE, SZ_1M, CFG_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_DUIO_BASE, SZ_64K, CFG_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB-entry for NAND */
- tlbentry( CFG_NAND0_ADDR, SZ_1K, CFG_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_NAND1_ADDR, SZ_1K, CFG_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB-entry for Internal Registers & OCM */
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds
index b20fb1c..05152b7 100644
--- a/board/esd/du440/u-boot.lds
+++ b/board/esd/du440/u-boot.lds
@@ -135,9 +135,10 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/hh405/flash.c
+++ b/board/esd/hh405/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -91,7 +91,7 @@ unsigned long flash_init (void)
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
index 802491a..efadf16 100644
--- a/board/esd/hh405/hh405.c
+++ b/board/esd/hh405/hh405.c
@@ -345,7 +345,7 @@ int board_early_init_f (void)
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, CFG_UIC0_POLARITY);/* set int polarities */
+ mtdcr(uicpr, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
@@ -363,26 +363,26 @@ int cf_enable(void)
int i;
volatile unsigned short *fpga_ctrl =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
volatile unsigned short *fpga_status =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2);
if (gd->board_type >= 2) {
- if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) {
- if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) {
- *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN;
+ if (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT) {
+ if (!(*fpga_ctrl & CONFIG_SYS_FPGA_CTRL_CF_BUS_EN)) {
+ *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_PWRN;
for (i=0; i<300; i++)
udelay(1000);
- *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
+ *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_BUS_EN;
for (i=0; i<20; i++)
udelay(1000);
}
} else {
- *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN;
- *fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN;
+ *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_BUS_EN;
+ *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_PWRN;
}
}
@@ -392,11 +392,11 @@ int cf_enable(void)
int misc_init_r (void)
{
volatile unsigned short *fpga_ctrl =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
volatile unsigned short *lcd_contrast =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
volatile unsigned short *lcd_backlight =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
@@ -405,8 +405,8 @@ int misc_init_r (void)
char *str;
unsigned long contrast0 = 0xffffffff;
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
@@ -474,22 +474,22 @@ int misc_init_r (void)
/*
* Setup and enable EEPROM write protection
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
/*
* Reset touch-screen controller
*/
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
udelay(1000);
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST);
+ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
/*
* Enable power on PS/2 interface (with reset)
*/
- *fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR);
+ *fpga_ctrl &= ~(CONFIG_SYS_FPGA_CTRL_PS2_PWR);
for (i=0;i<500;i++)
udelay(1000);
- *fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR);
+ *fpga_ctrl |= (CONFIG_SYS_FPGA_CTRL_PS2_PWR);
/*
* Get contrast value from environment variable
@@ -512,11 +512,11 @@ int misc_init_r (void)
/*
* Switch backlight on
*/
- *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL;
+ *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL;
*lcd_backlight = 0x0000;
lcd_setup(1, 0);
- lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_1024_768_8bpp,
sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
logo_bmp_1024, sizeof(logo_bmp_1024));
@@ -524,11 +524,11 @@ int misc_init_r (void)
/*
* Switch backlight on
*/
- *fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL;
+ *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_VGA0_BL;
*lcd_backlight = 0x0000;
lcd_setup(1, 0);
- lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
logo_bmp_640, sizeof(logo_bmp_640));
@@ -545,7 +545,7 @@ int misc_init_r (void)
/*
* Switch backlight on
*/
- *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
+ *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE;
/*
* Set lcd clock (small epson)
*/
@@ -553,7 +553,7 @@ int misc_init_r (void)
udelay(100); /* wait for 100 us */
lcd_setup(0, 1);
- lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13705_320_240_8bpp,
sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
@@ -570,14 +570,14 @@ int misc_init_r (void)
/*
* Switch backlight on
*/
- *fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
+ *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE;
/*
* Set lcd clock (small epson), enable 1-wire interface
*/
- *fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE;
+ *fpga_ctrl |= LCD_CLK_08330 | CONFIG_SYS_FPGA_CTRL_OW_ENABLE;
lcd_setup(0, 1);
- lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13704_320_240_4bpp,
sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
@@ -643,48 +643,31 @@ int checkboard (void)
return 0;
}
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
volatile unsigned short *fpga_mode =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
volatile unsigned short *fpga_status =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2);
- if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) ||
+ if (((gd->board_type >= 2) && (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT)) ||
(gd->board_type < 2)) {
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) { /* assert RESET */
cf_enable();
- *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+ *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else { /* release RESET */
- *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+ *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET;
}
}
}
#endif /* CONFIG_IDE_RESET */
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
* 0: disable write
@@ -695,23 +678,23 @@ void ide_set_reset(int on)
*/
int eeprom_write_enable (unsigned dev_addr, int state)
{
- if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
return -1;
} else {
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+ state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
break;
}
}
@@ -725,21 +708,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (query) {
/* Query write access state. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0) {
puts ("Query of write access state failed.\n");
} else {
printf ("Write access for device 0x%0x is %sabled.\n",
- CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
} else {
/* Enable write access. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
}
if (state < 0) {
puts ("Setup of write access state failed.\n");
@@ -752,7 +735,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
"eepwren - Enable / disable / query EEPROM write access\n",
NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
#ifdef CONFIG_VIDEO_SM501
diff --git a/board/esd/hh405/u-boot.lds b/board/esd/hh405/u-boot.lds
index 21547ac..9697cc6 100644
--- a/board/esd/hh405/u-boot.lds
+++ b/board/esd/hh405/u-boot.lds
@@ -72,7 +72,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -143,6 +143,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/hub405/flash.c
+++ b/board/esd/hub405/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -91,7 +91,7 @@ unsigned long flash_init (void)
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c
index 03b87c9..8785e6c 100644
--- a/board/esd/hub405/hub405.c
+++ b/board/esd/hub405/hub405.c
@@ -101,13 +101,6 @@ int board_early_init_f (void)
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
@@ -132,23 +125,23 @@ int misc_init_r (void)
* Set RS232/RS422 control (RS232 = high on GPIO)
*/
val = in32(GPIO0_OR);
- val &= ~(CFG_UART2_RS232 | CFG_UART3_RS232 | CFG_UART4_RS232 | CFG_UART5_RS232);
+ val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 | CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232);
str = getenv("phys0");
if (!str || (str && (str[0] == '0')))
- val |= CFG_UART2_RS232;
+ val |= CONFIG_SYS_UART2_RS232;
str = getenv("phys1");
if (!str || (str && (str[0] == '0')))
- val |= CFG_UART3_RS232;
+ val |= CONFIG_SYS_UART3_RS232;
str = getenv("phys2");
if (!str || (str && (str[0] == '0')))
- val |= CFG_UART4_RS232;
+ val |= CONFIG_SYS_UART4_RS232;
str = getenv("phys3");
if (!str || (str && (str[0] == '0')))
- val |= CFG_UART5_RS232;
+ val |= CONFIG_SYS_UART5_RS232;
out32(GPIO0_OR, val);
@@ -181,9 +174,9 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
udelay(10); /* wait 10us */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
/*
@@ -227,14 +220,3 @@ int checkboard (void)
return 0;
}
-
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
diff --git a/board/esd/hub405/u-boot.lds b/board/esd/hub405/u-boot.lds
index f21c7aa..6908106 100644
--- a/board/esd/hub405/u-boot.lds
+++ b/board/esd/hub405/u-boot.lds
@@ -66,14 +66,14 @@ SECTIONS
cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/4xx_enet.o (.text)
+ drivers/net/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -143,6 +143,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/mecp5200/mecp5200.c b/board/esd/mecp5200/mecp5200.c
index 6d776b7..3192450 100644
--- a/board/esd/mecp5200/mecp5200.c
+++ b/board/esd/mecp5200/mecp5200.c
@@ -32,6 +32,7 @@
#include <mpc5xxx.h>
#include <pci.h>
#include <command.h>
+#include <netdev.h>
#include "mt46v16m16-75.h"
@@ -80,7 +81,7 @@ static void sdram_start(int hi_addr)
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
@@ -105,9 +106,9 @@ phys_size_t initdram(int board_type)
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size(CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size(CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
@@ -142,9 +143,9 @@ phys_size_t initdram(int board_type)
#if 0
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
- get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
- get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(0);
#endif
/* set SDRAM CS1 size according to the amount of RAM found */
@@ -174,14 +175,14 @@ void flash_preinit(void)
void flash_afterinit(ulong size)
{
- if (size == CFG_FLASH_SIZE) {
+ if (size == CONFIG_SYS_FLASH_SIZE) {
/* adjust mapping */
*(vu_long *) MPC5XXX_BOOTCS_START =
*(vu_long *) MPC5XXX_CS0_START =
- START_REG(CFG_BOOTCS_START | size);
+ START_REG(CONFIG_SYS_BOOTCS_START | size);
*(vu_long *) MPC5XXX_BOOTCS_STOP =
*(vu_long *) MPC5XXX_CS0_STOP =
- STOP_REG(CFG_BOOTCS_START | size, size);
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
}
}
@@ -259,3 +260,8 @@ void init_power_switch(void)
__asm__ volatile ("sync");
}
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c
index c3d8bec..e763a89 100644
--- a/board/esd/ocrtc/flash.c
+++ b/board/esd/ocrtc/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c
index 7b0edd5..35bfa95 100644
--- a/board/esd/ocrtc/ocrtc.c
+++ b/board/esd/ocrtc/ocrtc.c
@@ -62,13 +62,6 @@ int board_early_init_f (void)
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
/*
* Check Board Identity:
*/
@@ -99,28 +92,3 @@ int checkboard (void)
return (0);
}
-
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr (memcfga, mem_mb0cf);
- val = mfdcr (memcfgd);
-
-#if 0
- printf ("\nmb0cf=%x\n", val); /* test-only */
- printf ("strap=%x\n", mfdcr (strap)); /* test-only */
-#endif
-
- return (4 * 1024 * 1024 << ((val & 0x000e0000) >> 17));
-}
-
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
diff --git a/board/esd/ocrtc/u-boot.lds b/board/esd/ocrtc/u-boot.lds
index 5fb9699..1fb754c 100644
--- a/board/esd/ocrtc/u-boot.lds
+++ b/board/esd/ocrtc/u-boot.lds
@@ -72,7 +72,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -143,6 +143,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c
index 5c717e25..f558a2b 100644
--- a/board/esd/pci405/cmd_pci405.c
+++ b/board/esd/pci405/cmd_pci405.c
@@ -32,13 +32,9 @@
#include "pci405.h"
-
#if defined(CONFIG_CMD_BSP)
extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-extern int do_bootvx (cmd_tbl_t *, int, int, char *[]);
-unsigned long get_dcr(unsigned short);
-
/*
* Command loadpci: wait for signal from host and boot image.
@@ -97,33 +93,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
} else {
sprintf(addr, "%08x", *ptr);
-#if 0
- /*
- * Boot image
- */
- if (*ptr & 0x00000001) {
- /*
- * Boot VxWorks image via bootvx
- */
- addr[strlen(addr)-1] = '0';
- printf("\nBooting VxWorks-Image at addr 0x%s ...\n", addr);
- setenv("loadaddr", addr);
-
- local_args[0] = argv[0];
- local_args[1] = NULL;
- status = do_bootvx (cmdtp, 0, 1, local_args);
- } else {
- /*
- * Boot image via bootm (normally Linux)
- */
- printf("\nBooting Image at addr 0x%s ...\n", addr);
- setenv("loadaddr", addr);
-
- local_args[0] = argv[0];
- local_args[1] = NULL;
- status = do_bootm (cmdtp, 0, 1, local_args);
- }
-#else
/*
* Boot image via bootm
*/
@@ -133,7 +102,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
local_args[0] = argv[0];
local_args[1] = NULL;
status = do_bootm (cmdtp, 0, 1, local_args);
-#endif
}
return 0;
@@ -143,843 +111,4 @@ U_BOOT_CMD(
"loadpci - Wait for pci-image and boot it\n",
NULL
);
-
-#endif
-
-#if 1 /* test-only */
-int do_getpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned int val;
- int i;
-
- printf("\nPCI Configuration Regs for PPC405GP:");
- for (i=0; i<0x64; i+=4) {
- pci_read_config_dword(PCIDEVID_405GP, i, &val);
- if (!(i % 0x10)) {
- printf("\n%02x: ", i);
- }
- printf("%08x ", val);
- }
- printf("\n");
-
- return 0;
-}
-U_BOOT_CMD(
- getpci, 1, 1, do_getpci,
- "getpci - Print own pci configuration registers\n",
- NULL
-);
-
-int do_setpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned int addr;
- unsigned int val;
-
- addr = simple_strtol (argv[1], NULL, 16);
- val = simple_strtol (argv[2], NULL, 16);
-
- printf("\nWriting %08x to PCI reg %08x.\n", val, addr);
- pci_write_config_dword(PCIDEVID_405GP, addr, val);
-
- return 0;
-}
-U_BOOT_CMD(
- setpci, 3, 1, do_setpci,
- "setpci - Set one pci configuration lword\n",
- "<addr> <val>\n"
- " - Write pci configuration lword <val> to <addr>.\n"
-);
-
-int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- int i;
-
- printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
- for (i=0; i<=0x1e0; i++) {
- if (!(i % 0x8)) {
- printf("\n%04x ", i);
- }
- printf("%08lx ", get_dcr(i));
- }
- printf("\n");
-
- return 0;
-}
-U_BOOT_CMD(
- dumpdcr, 1, 1, do_dumpdcr,
- "dumpdcr - Dump all DCR registers\n",
- NULL
-);
-
-
-int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
- printf("\n%04x %08x ", 947, mfspr(947));
- printf("\n%04x %08x ", 9, mfspr(9));
- printf("\n%04x %08x ", 1014, mfspr(1014));
- printf("\n%04x %08x ", 1015, mfspr(1015));
- printf("\n%04x %08x ", 1010, mfspr(1010));
- printf("\n%04x %08x ", 957, mfspr(957));
- printf("\n%04x %08x ", 1008, mfspr(1008));
- printf("\n%04x %08x ", 1018, mfspr(1018));
- printf("\n%04x %08x ", 954, mfspr(954));
- printf("\n%04x %08x ", 950, mfspr(950));
- printf("\n%04x %08x ", 951, mfspr(951));
- printf("\n%04x %08x ", 981, mfspr(981));
- printf("\n%04x %08x ", 980, mfspr(980));
- printf("\n%04x %08x ", 982, mfspr(982));
- printf("\n%04x %08x ", 1012, mfspr(1012));
- printf("\n%04x %08x ", 1013, mfspr(1013));
- printf("\n%04x %08x ", 948, mfspr(948));
- printf("\n%04x %08x ", 949, mfspr(949));
- printf("\n%04x %08x ", 1019, mfspr(1019));
- printf("\n%04x %08x ", 979, mfspr(979));
- printf("\n%04x %08x ", 8, mfspr(8));
- printf("\n%04x %08x ", 945, mfspr(945));
- printf("\n%04x %08x ", 987, mfspr(987));
- printf("\n%04x %08x ", 287, mfspr(287));
- printf("\n%04x %08x ", 953, mfspr(953));
- printf("\n%04x %08x ", 955, mfspr(955));
- printf("\n%04x %08x ", 272, mfspr(272));
- printf("\n%04x %08x ", 273, mfspr(273));
- printf("\n%04x %08x ", 274, mfspr(274));
- printf("\n%04x %08x ", 275, mfspr(275));
- printf("\n%04x %08x ", 260, mfspr(260));
- printf("\n%04x %08x ", 276, mfspr(276));
- printf("\n%04x %08x ", 261, mfspr(261));
- printf("\n%04x %08x ", 277, mfspr(277));
- printf("\n%04x %08x ", 262, mfspr(262));
- printf("\n%04x %08x ", 278, mfspr(278));
- printf("\n%04x %08x ", 263, mfspr(263));
- printf("\n%04x %08x ", 279, mfspr(279));
- printf("\n%04x %08x ", 26, mfspr(26));
- printf("\n%04x %08x ", 27, mfspr(27));
- printf("\n%04x %08x ", 990, mfspr(990));
- printf("\n%04x %08x ", 991, mfspr(991));
- printf("\n%04x %08x ", 956, mfspr(956));
- printf("\n%04x %08x ", 284, mfspr(284));
- printf("\n%04x %08x ", 285, mfspr(285));
- printf("\n%04x %08x ", 986, mfspr(986));
- printf("\n%04x %08x ", 984, mfspr(984));
- printf("\n%04x %08x ", 256, mfspr(256));
- printf("\n%04x %08x ", 1, mfspr(1));
- printf("\n%04x %08x ", 944, mfspr(944));
- printf("\n");
-
- return 0;
-}
-U_BOOT_CMD(
- dumpspr, 1, 1, do_dumpspr,
- "dumpspr - Dump all SPR registers\n",
- NULL
-);
-
-
-#define PCI0_BRDGOPT1 0x4a
-#define plb0_acr 0x87
-
-int do_getplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned short val;
-
- printf("PLB0_ACR=%08lx\n", get_dcr(0x87));
- pci_read_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, &val);
- printf("PCI0_BRDGOPT1=%04x\n", val);
- printf("CCR0=%08x\n", mfspr(ccr0));
-
- return 0;
-}
-U_BOOT_CMD(
- getplb, 1, 1, do_getplb,
- "getplb - Dump all plb arbiter registers\n",
- NULL
-);
-
-int do_setplb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned int my_acr;
- unsigned int my_brdgopt1;
- unsigned int my_ccr0;
-
- my_acr = simple_strtol (argv[1], NULL, 16);
- my_brdgopt1 = simple_strtol (argv[2], NULL, 16);
- my_ccr0 = simple_strtol (argv[3], NULL, 16);
-
- mtdcr(plb0_acr, my_acr);
- pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, my_brdgopt1);
- mtspr(ccr0, my_ccr0);
-
- return 0;
-}
-U_BOOT_CMD(
- setplb, 4, 1, do_setplb,
- "setplb - Set all plb arbiter registers\n",
- "PLB0_ACR PCI0_BRDGOPT1 CCR0\n"
- " - Set all plb arbiter registers\n"
-);
-
-
-/***********************************************************************
- *
- * The following code is only for test purposes!!!!
- * Please ignore this ugly stuff!!!!!!!!!!!!!!!!!!!
- *
- ***********************************************************************/
-
-#define PCI_ADDR 0xc0000000
-
-int do_writepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned int addr;
- unsigned int size;
- unsigned int countmax;
- int i;
- int max;
- volatile unsigned long *ptr;
- volatile unsigned long val;
- int loopcount = 0;
- int test_pci_read = 0;
- int test_pci_cfg_write = 0;
- int test_sync = 0;
- int test_pci_pre_read = 0;
-
- addr = simple_strtol (argv[1], NULL, 16);
- size = simple_strtol (argv[2], NULL, 16);
- countmax = simple_strtol (argv[3], NULL, 16);
- if (countmax == 0)
- countmax = 1000;
-
- do_getplb(NULL, 0, 0, NULL);
-
-#if 0
- out32r(PMM0LA, 0);
- out32r(PMM0PCILA, 0);
- out32r(PMM0PCIHA, 0);
- out32r(PMM0MA, 0);
- out32r(PMM1LA, PCI_ADDR);
- out32r(PMM1PCILA, addr & 0xff000000);
- out32r(PMM1PCIHA, 0x00000000);
- out32r(PMM1MA, 0xff000001);
-#endif
-
- printf("PMM1LA =%08lx\n", in32r(PMM1LA));
- printf("PMM1MA =%08lx\n", in32r(PMM1MA));
- printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
- printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
-
- addr = PCI_ADDR | (addr & 0x00ffffff);
- printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
-
- max = size >> 2;
-
- pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
- val = *(ulong *)0x00000000;
- if (val & 0x00000008) {
- test_pci_pre_read = 1;
- printf("Running test with pre pci-memory-read access!\n");
- }
- if (val & 0x00000004) {
- test_sync = 1;
- printf("Running test with sync instruction!\n");
- }
- if (val & 0x00000001) {
- test_pci_read = 1;
- printf("Running test with pci-memory-read access!\n");
- }
- if (val & 0x00000002) {
- test_pci_cfg_write = 1;
- printf("Running test with pci-config-write access!\n");
- }
-
- while (1) {
-
- if (test_pci_pre_read) {
- /*
- * Read one value back
- */
- ptr = (volatile unsigned long *)addr;
- val = *ptr;
- }
-
- /*
- * Write some values to host via pci busmastering
- */
- ptr = (volatile unsigned long *)addr;
- for (i=0; i<max; i++) {
- *ptr++ = i;
- }
-
- if (test_sync) {
- /*
- * Sync previous writes
- */
- ppcSync();
- }
-
- if (test_pci_read) {
- /*
- * Read one value back
- */
- ptr = (volatile unsigned long *)addr;
- val = *ptr;
- }
-
- if (test_pci_cfg_write) {
- /*
- * Generate IRQ to host via config regs
- */
- pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00);
- }
-
- if (loopcount++ > countmax) {
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
-
- putc('.');
-
- loopcount = 0;
- }
- }
-
- return 0;
-}
-U_BOOT_CMD(
- writepci, 4, 1, do_writepci,
- "writepci - Write some data to pcibus\n",
- "<addr> <size>\n"
- " - Write some data to pcibus.\n"
-);
-
-#define PCI_CFGADDR 0xeec00000
-#define PCI_CFGDATA 0xeec00004
-
-int ibmPciConfigWrite
-(
- int offset, /* offset into the configuration space */
- int width, /* data width */
- unsigned int data /* data to be written */
- )
-{
- /*
- * Write config register address to the PCI config address register
- * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation)
- */
- out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC));
-
-#if 0 /* test-only */
- ppcSync();
-#endif
-
- /*
- * Write value to be written to the PCI config data register
- */
- switch ( width ) {
- case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF));
- break;
- case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF));
- break;
- case 4: out32r(PCI_CFGDATA | (offset & 0x3), data);
- break;
- }
-
- return (0);
-}
-
-int do_writepci2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned int addr;
- unsigned int size;
- unsigned int countmax;
- int max;
- volatile unsigned long *ptr;
- volatile unsigned long val;
- int loopcount = 0;
-
- addr = simple_strtol (argv[1], NULL, 16);
- size = simple_strtol (argv[2], NULL, 16);
- countmax = simple_strtol (argv[3], NULL, 16);
- if (countmax == 0)
- countmax = 1000;
-
- do_getplb(NULL, 0, 0, NULL);
-
-#if 0
- out32r(PMM0LA, 0);
- out32r(PMM0PCILA, 0);
- out32r(PMM0PCIHA, 0);
- out32r(PMM0MA, 0);
- out32r(PMM1LA, PCI_ADDR);
- out32r(PMM1PCILA, addr & 0xff000000);
- out32r(PMM1PCIHA, 0x00000000);
- out32r(PMM1MA, 0xff000001);
-#endif
-
- printf("PMM1LA =%08lx\n", in32r(PMM1LA));
- printf("PMM1MA =%08lx\n", in32r(PMM1MA));
- printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
- printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
-
- addr = PCI_ADDR | (addr & 0x00ffffff);
- printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
-
- max = size >> 2;
-
- pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
- while (1) {
-
- /*
- * Write one values to host via pci busmastering
- */
- ptr = (volatile unsigned long *)addr;
- *ptr = 0x01234567;
-
- /*
- * Read one value back
- */
- ptr = (volatile unsigned long *)addr;
- val = *ptr;
-
- /*
- * One pci config write
- */
-/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
-/* ibmPciConfigWrite(0x44, 1, 0x00); */
- ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */
-
- if (loopcount++ > countmax) {
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
-
- putc('.');
-
- loopcount = 0;
- }
- }
-
- return 0;
-}
-U_BOOT_CMD(
- writepci2, 4, 1, do_writepci2,
- "writepci2- Write some data to pcibus\n",
- "<addr> <size>\n"
- " - Write some data to pcibus.\n"
-);
-
-int do_writepci22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned int addr;
- unsigned int size;
- unsigned int countmax = 0;
- volatile unsigned long *ptr;
- volatile unsigned long val;
-
- addr = simple_strtol (argv[1], NULL, 16);
- size = simple_strtol (argv[2], NULL, 16);
-
- addr = PCI_ADDR | (addr & 0x00ffffff);
- printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
- pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
- while (1) {
-
- /*
- * Write one values to host via pci busmastering
- */
- ptr = (volatile unsigned long *)addr;
- *ptr = 0x01234567;
-
- /*
- * Read one value back
- */
- ptr = (volatile unsigned long *)addr;
- val = *ptr;
-
- /*
- * One pci config write
- */
- ibmPciConfigWrite(0x2e, 2, 0x1234); /* subsystem id */
- }
-
- return 0;
-}
-U_BOOT_CMD(
- writepci22, 4, 1, do_writepci22,
- "writepci22- Write some data to pcibus\n",
- "<addr> <size>\n"
- " - Write some data to pcibus.\n"
-);
-
-int ibmPciConfigWrite3
-(
- int offset, /* offset into the configuration space */
- int width, /* data width */
- unsigned int data /* data to be written */
- )
-{
- /*
- * Write config register address to the PCI config address register
- * bit 31 must be 1 and bits 1:0 must be 0 (note LE bit notation)
- */
- out32r(PCI_CFGADDR, 0x80000000 | (offset & 0xFFFFFFFC));
-
-#if 1 /* test-only */
- ppcSync();
-#endif
-
- /*
- * Write value to be written to the PCI config data register
- */
- switch ( width ) {
- case 1: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned char)(data & 0xFF));
- break;
- case 2: out32r(PCI_CFGDATA | (offset & 0x3), (unsigned short)(data & 0xFFFF));
- break;
- case 4: out32r(PCI_CFGDATA | (offset & 0x3), data);
- break;
- }
-
- return (0);
-}
-
-int do_writepci3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned int addr;
- unsigned int size;
- unsigned int countmax;
- int max;
- volatile unsigned long *ptr;
- volatile unsigned long val;
- int loopcount = 0;
-
- addr = simple_strtol (argv[1], NULL, 16);
- size = simple_strtol (argv[2], NULL, 16);
- countmax = simple_strtol (argv[3], NULL, 16);
- if (countmax == 0)
- countmax = 1000;
-
- do_getplb(NULL, 0, 0, NULL);
-
-#if 0
- out32r(PMM0LA, 0);
- out32r(PMM0PCILA, 0);
- out32r(PMM0PCIHA, 0);
- out32r(PMM0MA, 0);
- out32r(PMM1LA, PCI_ADDR);
- out32r(PMM1PCILA, addr & 0xff000000);
- out32r(PMM1PCIHA, 0x00000000);
- out32r(PMM1MA, 0xff000001);
-#endif
-
- printf("PMM1LA =%08lx\n", in32r(PMM1LA));
- printf("PMM1MA =%08lx\n", in32r(PMM1MA));
- printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
- printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
-
- addr = PCI_ADDR | (addr & 0x00ffffff);
- printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
-
- max = size >> 2;
-
- pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
- while (1) {
-
- /*
- * Write one values to host via pci busmastering
- */
- ptr = (volatile unsigned long *)addr;
- *ptr = 0x01234567;
-
- /*
- * Read one value back
- */
- ptr = (volatile unsigned long *)addr;
- val = *ptr;
-
- /*
- * One pci config write
- */
-/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
-/* ibmPciConfigWrite(0x44, 1, 0x00); */
- ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */
-
- if (loopcount++ > countmax) {
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
-
- putc('.');
-
- loopcount = 0;
- }
- }
-
- return 0;
-}
-U_BOOT_CMD(
- writepci3, 4, 1, do_writepci3,
- "writepci3- Write some data to pcibus\n",
- "<addr> <size>\n"
- " - Write some data to pcibus.\n"
-);
-
-
-#define SECTOR_SIZE 32 /* 32 byte cache line */
-#define SECTOR_MASK 0x1F
-
-void my_flush_dcache(ulong lcl_addr, ulong count)
-{
- unsigned int lcl_target;
-
- /* promote to nearest cache sector */
- lcl_target = (lcl_addr + count + SECTOR_SIZE - 1) & ~SECTOR_MASK;
- lcl_addr &= ~SECTOR_MASK;
- while (lcl_addr != lcl_target)
- {
- /* ppcDcbf((void *)lcl_addr);*/
- __asm__("dcbf 0,%0": :"r" (lcl_addr));
- lcl_addr += SECTOR_SIZE;
- }
- __asm__("sync"); /* Always flush prefetch queue in any case */
-}
-
-int do_writepci_cache(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned int addr;
- unsigned int size;
- unsigned int countmax;
- int i;
- volatile unsigned long *ptr;
- volatile unsigned long val;
- int loopcount = 0;
-
- addr = simple_strtol (argv[1], NULL, 16);
- size = simple_strtol (argv[2], NULL, 16);
- countmax = simple_strtol (argv[3], NULL, 16);
- if (countmax == 0)
- countmax = 1000;
-
- do_getplb(NULL, 0, 0, NULL);
-
-#if 0
- out32r(PMM0LA, 0);
- out32r(PMM0PCILA, 0);
- out32r(PMM0PCIHA, 0);
- out32r(PMM0MA, 0);
- out32r(PMM1LA, PCI_ADDR);
- out32r(PMM1PCILA, addr & 0xff000000);
- out32r(PMM1PCIHA, 0x00000000);
- out32r(PMM1MA, 0xff000001);
-#endif
-
- printf("PMM1LA =%08lx\n", in32r(PMM1LA));
- printf("PMM1MA =%08lx\n", in32r(PMM1MA));
- printf("PMM1PCILA =%08lx\n", in32r(PMM1PCILA));
- printf("PMM1PCIHA =%08lx\n", in32r(PMM1PCIHA));
-
- addr = PCI_ADDR | (addr & 0x00ffffff);
- printf("\nWriting at addr %08x, size %08x (countmax=%x)\n", addr, size, countmax);
-
- pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
- i = 0;
-
- /*
- * Set pci region as cachable
- */
- ppcSync();
- __asm__ volatile (" addis 4,0,0x0000 ");
- __asm__ volatile (" addi 4,4,0x0080 ");
- __asm__ volatile (" mtdccr 4 ");
- ppcSync();
-
- while (1) {
-
- /*
- * Write one values to host via pci busmastering
- */
- ptr = (volatile unsigned long *)addr;
- printf("A\n"); /* test-only */
- *ptr++ = i++;
- *ptr++ = i++;
- *ptr++ = i++;
- *ptr++ = i++;
- *ptr++ = i++;
- *ptr++ = i++;
- *ptr++ = i++;
- *ptr++ = i++;
- printf("B\n"); /* test-only */
- my_flush_dcache(addr, 32);
- printf("C\n"); /* test-only */
-
- /*
- * Read one value back
- */
- ptr = (volatile unsigned long *)addr;
- val = *ptr;
- printf("D\n"); /* test-only */
-
- /*
- * One pci config write
- */
-/* pci_write_config_byte(PCIDEVID_405GP, 0x44, 0x00); */
-/* ibmPciConfigWrite(0x44, 1, 0x00); */
- ibmPciConfigWrite3(0x2e, 2, 0x1234); /* subsystem id */
- printf("E\n"); /* test-only */
-
- if (loopcount++ > countmax) {
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
-
- putc('.');
-
- loopcount = 0;
- }
- }
-
- return 0;
-}
-U_BOOT_CMD(
- writepci_cache, 4, 1, do_writepci_cache,
- "writepci_cache - Write some data to pcibus\n",
- "<addr> <size>\n"
- " - Write some data to pcibus.\n"
-);
-
-int do_savepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned int *ptr;
- int i;
-
- /*
- * Save own pci configuration in PRAM
- */
- memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
- ptr = (unsigned int *)PCI_REGS_ADDR + 1;
- for (i=0; i<0x40; i+=4) {
- pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
- }
- ptr = (unsigned int *)PCI_REGS_ADDR;
- *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
-
- printf("\nStoring PCI Configuration Regs...\n");
-
- return 0;
-}
-U_BOOT_CMD(
- savepci, 4, 1, do_savepci,
- "savepci - Save all pci regs\n",
- "<addr> <size>\n"
- " - Write some data to pcibus.\n"
-);
-
-int do_restorepci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned int *ptr;
- int i;
-
- /*
- * Rewrite pci config regs (only after soft-reset with magic set)
- */
- ptr = (unsigned int *)PCI_REGS_ADDR;
- if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
- puts("Restoring PCI Configurations Regs!\n");
- ptr = (unsigned int *)PCI_REGS_ADDR + 1;
- for (i=0; i<0x40; i+=4) {
- pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
- }
- }
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-
- return 0;
-}
-U_BOOT_CMD(
- restorepci, 4, 1, do_restorepci,
- "restorepci - Restore all pci regs\n",
- "<addr> <size>\n"
- " - Write some data to pcibus.\n"
-);
-
-
-extern void write_without_sync(void);
-extern void write_with_sync(void);
-extern void write_with_less_sync(void);
-extern void write_with_more_sync(void);
-
-/*
- * code from IBM-PPCSUPP
- */
-int do_writeibm1(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
- write_without_sync();
-
- return 0;
-}
-U_BOOT_CMD(
- writeibm1, 4, 1, do_writeibm1,
- "writeibm1- Write some data to pcibus (without sync)\n",
- "<addr> <size>\n"
- " - Write some data to pcibus.\n"
-);
-
-int do_writeibm2(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
- write_with_sync();
-
- return 0;
-}
-U_BOOT_CMD(
- writeibm2, 4, 1, do_writeibm2,
- "writeibm2- Write some data to pcibus (with sync)\n",
- "<addr> <size>\n"
- " - Write some data to pcibus.\n"
-);
-
-int do_writeibm22(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
- write_with_less_sync();
-
- return 0;
-}
-U_BOOT_CMD(
- writeibm22, 4, 1, do_writeibm22,
- "writeibm22- Write some data to pcibus (with less sync)\n",
- "<addr> <size>\n"
- " - Write some data to pcibus.\n"
-);
-
-int do_writeibm3(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- pci_write_config_word(PCIDEVID_405GP, 0x04, 0x0106); /* write command reg */
-
- write_with_more_sync();
-
- return 0;
-}
-U_BOOT_CMD(
- writeibm3, 4, 1, do_writeibm3,
- "writeibm3- Write some data to pcibus (with more sync)\n",
- "<addr> <size>\n"
- " - Write some data to pcibus.\n"
-);
#endif
diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c
index 3b21781..9058483 100644
--- a/board/esd/pci405/flash.c
+++ b/board/esd/pci405/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
index f740d59..42774ad 100644
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@@ -27,6 +27,7 @@
#include <malloc.h>
#include <pci.h>
#include <asm/4xx_pci.h>
+#include <asm/io.h>
#include "pci405.h"
@@ -34,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Prototypes */
int gunzip(void *, int, unsigned char *, unsigned long *);
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
unsigned long fpga_done_state(void);
unsigned long fpga_init_state(void);
@@ -57,11 +58,11 @@ const unsigned char fpgadata[] =
*/
#include "../common/fpga.c"
-#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_DONE)
-#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_DONE_V12)
+#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
-#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_INIT)
-#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_INIT_V12)
+#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
+#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
int board_revision(void)
@@ -78,10 +79,10 @@ int board_revision(void)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
- out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200);
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
udelay(1000); /* wait some time before reading input */
- value = in32(GPIO0_IR) & 0x00100200; /* get config bits */
+ value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
/*
* Restore GPIO settings
@@ -137,10 +138,10 @@ int board_early_init_f (void)
/*
* First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
*/
- out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
- out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
- out32(GPIO0_OR, 0); /* pull prg low */
+ out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+ out_be32((void*)GPIO0_OR, 0); /* pull prg low */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
@@ -181,15 +182,6 @@ int board_early_init_f (void)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
unsigned char *dst;
@@ -205,8 +197,8 @@ int misc_init_r (void)
* FPGA can be gzip compressed (malloc) and booted this late.
*/
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
@@ -284,13 +276,11 @@ int misc_init_r (void)
*magic = 0; /* clear pci reconfig magic again */
}
-#if 1 /* test-only */
/*
* Decrease PLB latency timeout and reduce priority of the PCI bridge master
*/
#define PCI0_BRDGOPT1 0x4a
pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
-/* pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60); */
#define plb0_acr 0x87
/*
@@ -298,14 +288,6 @@ int misc_init_r (void)
*/
mtdcr(plb0_acr, 0x98000000);
-#if 0 /* test-only */
- printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */
-/* mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000); */
- mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000);
-#endif
-/* printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */
-#endif
-
free(dst);
return (0);
}
@@ -314,7 +296,6 @@ int misc_init_r (void)
/*
* Check Board Identity:
*/
-
int checkboard (void)
{
char str[64];
@@ -340,14 +321,14 @@ int checkboard (void)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
- out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000);
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
udelay(1000); /* wait some time before reading input */
- value = in32(GPIO0_IR) & 0x40000000; /* get config bits */
+ value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */
if (value) {
puts(", 33 MHz PCI");
} else {
- puts(", 66 Mhz PCI");
+ puts(", 66 MHz PCI");
}
}
@@ -357,37 +338,6 @@ int checkboard (void)
}
/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
-#if 0 /* test-only: all PCI405 version must report 16mb */
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-#else
- return (16*1024*1024);
-#endif
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
int wpeeprom(int wp)
{
int wp_state = wp;
diff --git a/board/esd/pci405/u-boot.lds b/board/esd/pci405/u-boot.lds
index 21547ac..9697cc6 100644
--- a/board/esd/pci405/u-boot.lds
+++ b/board/esd/pci405/u-boot.lds
@@ -72,7 +72,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -143,6 +143,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c
index 53afbc0..9850445 100644
--- a/board/esd/pf5200/flash.c
+++ b/board/esd/pf5200/flash.c
@@ -23,7 +23,7 @@
#include <common.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
typedef unsigned short FLASH_PORT_WIDTH;
typedef volatile unsigned short FLASH_PORT_WIDTHV;
@@ -60,7 +60,7 @@ unsigned long flash_init(void)
extern void flash_preinit(void);
extern void flash_afterinit(uint, ulong, ulong);
- ulong flashbase = CFG_FLASH_BASE;
+ ulong flashbase = CONFIG_SYS_FLASH_BASE;
flash_preinit();
@@ -69,18 +69,18 @@ unsigned long flash_init(void)
flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
size += flash_info[i].size;
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + monitor_flash_len - 1,
- flash_get_info(CFG_MONITOR_BASE));
+ flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ flash_get_info(CONFIG_SYS_MONITOR_BASE));
#endif
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
- flash_get_info(CFG_ENV_ADDR));
+ flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+ flash_get_info(CONFIG_ENV_ADDR));
#endif
flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
@@ -107,14 +107,14 @@ static flash_info_t *flash_get_info(ulong base) {
int i;
flash_info_t *info;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
info = &flash_info[i];
if ((info->size) && (info->start[0] <= base)
&& (base <= info->start[0] + info->size - 1)) {
break;
}
}
- return (i == CFG_MAX_FLASH_BANKS ? 0 : info);
+ return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
}
/*-----------------------------------------------------------------------
@@ -336,7 +336,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) {
udelay(1000);
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
if (intel) {
/* suspend erase */
@@ -347,14 +347,14 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) {
break;
}
/* show that we're waiting */
- if ((get_timer(last)) > CFG_HZ) {
+ if ((get_timer(last)) > CONFIG_SYS_HZ) {
/* every second */
putc('.');
last = get_timer(0);
}
}
/* show that we're waiting */
- if ((get_timer(last)) > CFG_HZ) {
+ if ((get_timer(last)) > CONFIG_SYS_HZ) {
/* every second */
putc('.');
last = get_timer(0);
@@ -452,7 +452,7 @@ static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
/* data polling for D7 */
while (res == 0
&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW) 0x00F000F0; /* reset bank */
res = 1;
}
diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c
index 7970f89..f7962af 100644
--- a/board/esd/pf5200/pf5200.c
+++ b/board/esd/pf5200/pf5200.c
@@ -32,6 +32,7 @@
#include <mpc5xxx.h>
#include <pci.h>
#include <command.h>
+#include <netdev.h>
#include "mt46v16m16-75.h"
@@ -80,7 +81,7 @@ static void sdram_start(int hi_addr)
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
@@ -105,9 +106,9 @@ phys_size_t initdram(int board_type)
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
@@ -143,9 +144,9 @@ phys_size_t initdram(int board_type)
#if 0
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
- get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
- get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(0);
#endif
/* set SDRAM CS1 size according to the amount of RAM found */
@@ -179,10 +180,10 @@ void flash_afterinit(ulong size)
/* adjust mapping */
*(vu_long *) MPC5XXX_BOOTCS_START =
*(vu_long *) MPC5XXX_CS0_START =
- START_REG(CFG_BOOTCS_START | size);
+ START_REG(CONFIG_SYS_BOOTCS_START | size);
*(vu_long *) MPC5XXX_BOOTCS_STOP =
*(vu_long *) MPC5XXX_CS0_STOP =
- STOP_REG(CFG_BOOTCS_START | size, size);
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
}
}
@@ -257,13 +258,18 @@ void init_power_switch(void)
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
__asm__ volatile ("sync");
}
- *(vu_char *) CFG_CS1_START = 0x02; /* Red Power LED on */
+ *(vu_char *) CONFIG_SYS_CS1_START = 0x02; /* Red Power LED on */
__asm__ volatile ("sync");
- *(vu_char *) (CFG_CS1_START + 1) = 0x02; /* Disable driver for KB11 */
+ *(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02; /* Disable driver for KB11 */
__asm__ volatile ("sync");
}
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
void power_set_reset(int power)
{
debug("ide_set_reset(%d)\n", power);
diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk
index 25b2105..0fb4efa 100644
--- a/board/esd/plu405/config.mk
+++ b/board/esd/plu405/config.mk
@@ -25,5 +25,4 @@
# esd PLU405 boards
#
-TEXT_BASE = 0xFFFC0000
-#TEXT_BASE = 0x00FC0000
+TEXT_BASE = 0xFFFA0000
diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/plu405/flash.c
+++ b/board/esd/plu405/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -91,7 +91,7 @@ unsigned long flash_init (void)
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index fc71e9a..61186a8 100644
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -65,11 +65,9 @@ au_image_t au_image[] = {
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
-
/* Prototypes */
int gunzip(void *, int, unsigned char *, unsigned long *);
-
int board_early_init_f (void)
{
/*
@@ -89,24 +87,18 @@ int board_early_init_f (void)
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
/*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ * EBC Configuration Register: set ready timeout to
+ * 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
@@ -121,8 +113,8 @@ int misc_init_r (void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
@@ -132,13 +124,16 @@ int misc_init_r (void)
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ printf("(Timeout: INIT not low "
+ "after asserting PROGRAM*)\n");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ printf("(Timeout: INIT not high "
+ "after deasserting PROGRAM*)\n");
break;
case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
+ printf("(Timeout: DONE not high "
+ "after programming FPGA)\n");
break;
}
@@ -184,22 +179,23 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
- udelay(10); /* wait 10us */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
- udelay(1000); /* wait 1ms */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
+ udelay(10);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
+ udelay(1000);
/*
* Set NAND-FLASH GPIO signals to default
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
/*
* Setup EEPROM write protection
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
/*
* Enable interrupts in exar duart mcr[3]
@@ -210,7 +206,6 @@ int misc_init_r (void)
return (0);
}
-
/*
* Check Board Identity:
*/
@@ -231,36 +226,23 @@ int checkboard (void)
return 0;
}
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
volatile unsigned short *fpga_mode =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) { /* assert RESET */
- *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+ *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else { /* release RESET */
- *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+ *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET;
}
}
#endif /* CONFIG_IDE_RESET */
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
@@ -272,8 +254,7 @@ void reset_phy(void)
#endif
}
-
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
* 0: disable write
@@ -284,23 +265,26 @@ void reset_phy(void)
*/
int eeprom_write_enable (unsigned dev_addr, int state)
{
- if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
return -1;
} else {
switch (state) {
case 1:
/* Enable write access, clear bit GPIO0. */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO0. */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
+ state = (0 == (in_be32((void*)GPIO0_OR) &
+ CONFIG_SYS_EEPROM_WP));
break;
}
}
@@ -314,21 +298,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (query) {
/* Query write access state. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0) {
puts ("Query of write access state failed.\n");
} else {
printf ("Write access for device 0x%0x is %sabled.\n",
- CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
} else {
/* Enable write access. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
}
if (state < 0) {
puts ("Setup of write access state failed.\n");
@@ -341,4 +325,4 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
"eepwren - Enable / disable / query EEPROM write access\n",
NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/plu405/u-boot.lds b/board/esd/plu405/u-boot.lds
index d70d379..fd5f3df 100644
--- a/board/esd/plu405/u-boot.lds
+++ b/board/esd/plu405/u-boot.lds
@@ -61,19 +61,6 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
@@ -124,7 +111,6 @@ SECTIONS
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
-
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
@@ -144,6 +130,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
index 326d560..c0781dc 100644
--- a/board/esd/pmc405/pmc405.c
+++ b/board/esd/pmc405/pmc405.c
@@ -72,23 +72,23 @@ int board_early_init_f (void)
* Setup GPIO pins
*/
- mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \
- CFG_FPGA_DONE | \
- CFG_XEREADY | \
- CFG_NONMONARCH | \
- CFG_REV1_2) << 5));
+ mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \
+ CONFIG_SYS_FPGA_DONE | \
+ CONFIG_SYS_XEREADY | \
+ CONFIG_SYS_NONMONARCH | \
+ CONFIG_SYS_REV1_2) << 5));
- if (!(in32(GPIO0_IR) & CFG_REV1_2)) {
+ if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) {
/* rev 1.2 boards */
- mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \
- CFG_SELF_RST) << 5));
+ mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \
+ CONFIG_SYS_SELF_RST) << 5));
}
out32(GPIO0_OR, 0);
- out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */
+ out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */
/* - check if rev1_2 is low, then:
- * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST#
+ * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST#
*/
return 0;
@@ -104,7 +104,7 @@ int misc_init_r (void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */
+ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); /* deassert EREADY# */
return (0);
}
@@ -112,13 +112,13 @@ ushort pmc405_pci_subsys_deviceid(void)
{
ulong val;
val = in32(GPIO0_IR);
- if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
- if (val & CFG_NONMONARCH) { /* monarch# signal */
- return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
+ if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
+ if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
+ return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
}
- return CFG_PCI_SUBSYS_DEVICEID_MONARCH;
+ return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
}
- return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
+ return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
}
/*
@@ -140,9 +140,9 @@ int checkboard (void)
}
val = in32(GPIO0_IR);
- if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
+ if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
puts(" rev1.2 (");
- if (val & CFG_NONMONARCH) { /* monarch# signal */
+ if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
puts("non-");
}
puts("monarch)");
@@ -156,24 +156,6 @@ int checkboard (void)
}
/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-
-/* ------------------------------------------------------------------------- */
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
diff --git a/board/esd/pmc405/u-boot.lds b/board/esd/pmc405/u-boot.lds
index 81ee614..ca615f5 100644
--- a/board/esd/pmc405/u-boot.lds
+++ b/board/esd/pmc405/u-boot.lds
@@ -72,7 +72,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -142,6 +142,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
index ca5c177..16c9c7e 100644
--- a/board/esd/pmc440/cmd_pmc440.c
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -26,6 +26,9 @@
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/processor.h>
+#if defined(CONFIG_LOGBUFFER)
+#include <logbuff.h>
+#endif
#include "pmc440.h"
@@ -323,7 +326,7 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]
}
printf("Writing boot EEPROM ...\n");
- if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
+ if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
0, (uchar*)sdsdp, count) != 0)
printf("bootstrap_eeprom_write failed\n");
else
@@ -343,14 +346,11 @@ extern env_t *env_ptr;
int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- u32 memsize;
- u32 pram, env_base;
+ u32 pram, nextbase, base;
char *v;
u32 param;
ulong *lptr;
- memsize = gd->bd->bi_memsize;
-
v = getenv("pram");
if (v)
pram = simple_strtoul(v, NULL, 10);
@@ -359,21 +359,42 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
- param = memsize - (pram << 10);
+ base = gd->bd->bi_memsize;
+#if defined(CONFIG_LOGBUFFER)
+ base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
+#endif
+ /*
+ * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
+ */
+ param = base - (pram << 10);
printf("PARAM: @%08x\n", param);
+ debug("memsize=0x%08x, base=0x%08x\n", gd->bd->bi_memsize, base);
+ /* clear entire PA ram */
memset((void*)param, 0, (pram << 10));
- env_base = memsize - 4096 - ((CFG_ENV_SIZE + 4096) & ~(4096-1));
- memcpy((void*)env_base, env_ptr, CFG_ENV_SIZE);
- lptr = (ulong*)memsize;
- *(--lptr) = CFG_ENV_SIZE;
- *(--lptr) = memsize - env_base;
- *(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08);
- *(--lptr) = 0;
+ /* reserve 4k for pointer field */
+ nextbase = base - 4096;
+ lptr = (ulong*)(base);
+
+ /*
+ * *(--lptr) = item_size;
+ * *(--lptr) = base - item_base = distance from field top;
+ */
+
+ /* env is first (4k aligned) */
+ nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
+ memcpy((void*)nextbase, env_ptr, CONFIG_ENV_SIZE);
+ *(--lptr) = CONFIG_ENV_SIZE; /* size */
+ *(--lptr) = base - nextbase; /* offset | type=0 */
+
+ /* free section */
+ *(--lptr) = nextbase - param; /* size */
+ *(--lptr) = (base - param) | 126; /* offset | type=126 */
- /* make sure data can be accessed through PCI */
- flush_dcache_range(param, param + (pram << 10) - 1);
+ /* terminate pointer field */
+ *(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
+ *(--lptr) = 0; /* offset=0 -> terminator */
return 0;
}
U_BOOT_CMD(
@@ -385,28 +406,11 @@ U_BOOT_CMD(
int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- if (argc > 1) {
- if (argv[1][0] == '0') {
- /* assert */
- printf("self-reset# asserted\n");
- out_be32((void*)GPIO0_TCR,
- in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST);
- } else {
- /* deassert */
- printf("self-reset# deasserted\n");
- out_be32((void*)GPIO0_TCR,
- in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST);
- }
- } else {
- printf("self-reset# is %s\n",
- in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ?
- "active" : "inactive");
- }
-
+ in_be32((void*)CONFIG_SYS_RESET_BASE);
return 0;
}
U_BOOT_CMD(
- selfreset, 2, 1, do_selfreset,
+ selfreset, 1, 1, do_selfreset,
"selfreset- assert self-reset# signal\n",
NULL
);
@@ -513,7 +517,7 @@ U_BOOT_CMD(
"<pciaddr> (pciaddr will be aligned to 256MB)\n"
);
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int query = argc == 1;
@@ -521,21 +525,21 @@ int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (query) {
/* Query write access state. */
- state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0) {
puts("Query of write access state failed.\n");
} else {
printf("Write access for device 0x%0x is %sabled.\n",
- CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
- state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
} else {
/* Enable write access. */
- state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
+ state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
}
if (state < 0) {
puts("Setup of write access state failed.\n");
@@ -547,6 +551,6 @@ int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
"eepwren - Enable / disable / query EEPROM write access\n",
NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
#endif /* CONFIG_CMD_BSP */
diff --git a/board/esd/pmc440/config.mk b/board/esd/pmc440/config.mk
index e62b8d3..0c4d582 100644
--- a/board/esd/pmc440/config.mk
+++ b/board/esd/pmc440/config.mk
@@ -37,5 +37,5 @@ PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c
index a35f42b..a2eda32 100644
--- a/board/esd/pmc440/fpga.c
+++ b/board/esd/pmc440/fpga.c
@@ -220,8 +220,9 @@ int fpga_post_config_fn(int cookie)
FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
- /* NGCC only: enable ledlink */
- if ((s = getenv("bd_type")) && !strcmp(s, "ngcc"))
+ /* NGCC/CANDES only: enable ledlink */
+ if ((s = getenv("bd_type")) &&
+ ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes"))))
FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
return rc;
diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
index 148af71..26a8282 100644
--- a/board/esd/pmc440/init.S
+++ b/board/esd/pmc440/init.S
@@ -44,28 +44,28 @@ tlbtab:
* speed up boot process. It is patched after relocation to enable SA_I
*/
#ifndef CONFIG_NAND_SPL
- tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
#else
- tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
#endif
/* TLB-entry for DDR SDRAM (Up to 2GB) */
#ifdef CONFIG_4xx_DCACHE
- tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
#else
- tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
#endif
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
#endif
/* TLB-entry for PCI Memory */
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
/* TLB-entries for EBC */
/* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
@@ -76,7 +76,7 @@ tlbtab:
tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB-entry for NAND */
- tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
/* TLB-entry for Internal Registers & OCM */
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
@@ -98,8 +98,8 @@ tlbtab:
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
-#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
+#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
.globl reconfig_tlb0
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 0cdaee4..3824105 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007-2008
+ * (Cg) Copyright 2007-2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
* Based on board/amcc/sequoia/sequoia.c
*
@@ -44,10 +44,12 @@
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern void __ft_board_setup(void *blob, bd_t *bd);
ulong flash_get_size(ulong base, int banknum);
int pci_is_66mhz(void);
+int is_monarch(void);
int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
uchar *buffer, unsigned cnt);
@@ -71,7 +73,7 @@ struct serial_device *default_serial_console(void)
/* mark scratchreg valid */
scratchreg = (scratchreg & 0xffffff00) | 0x80;
- i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR,
+ i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
0x10, buf, 4);
if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
scratchreg |= buf[2];
@@ -103,13 +105,13 @@ int board_early_init_f(void)
/*
* Setup the GPIO pins
- * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file
+ * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
*/
- out32(GPIO0_OR, 0x40000002);
+ out32(GPIO0_OR, 0x40000102);
out32(GPIO0_TCR, 0x4c90011f);
- out32(GPIO0_OSRL, 0x28011400);
+ out32(GPIO0_OSRL, 0x28051400);
out32(GPIO0_OSRH, 0x55005000);
- out32(GPIO0_TSRL, 0x08011400);
+ out32(GPIO0_TSRL, 0x08051400);
out32(GPIO0_TSRH, 0x55005000);
out32(GPIO0_ISR1L, 0x54000000);
out32(GPIO0_ISR1H, 0x00000000);
@@ -190,12 +192,29 @@ int board_early_init_f(void)
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
- (0x80000000 >> (28 + CFG_NAND_CS));
+ (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
return 0;
}
+#if defined(CONFIG_MISC_INIT_F)
+int misc_init_f(void)
+{
+ struct pci_controller hose;
+ hose.first_busno = 0;
+ hose.last_busno = 0;
+ hose.region_count = 0;
+
+ if (getenv("pciearly") && (!is_monarch())) {
+ printf("PCI: early target init\n");
+ pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA);
+ pci_target_init(&hose);
+ }
+ return 0;
+}
+#endif
+
/*
* misc_init_r.
*/
@@ -207,6 +226,7 @@ int misc_init_r(void)
unsigned long usb2d0cr = 0;
unsigned long usb2phy0cr, usb2h0cr = 0;
unsigned long sdr0_pfc1;
+ unsigned long sdr0_srst0, sdr0_srst1;
char *act = getenv("usbact");
/*
@@ -239,24 +259,24 @@ int misc_init_r(void)
*/
flash_get_size(gd->bd->bi_flashstart, 0);
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
/* Env protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR_REDUND,
- CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
/*
* USB suff...
*/
- if ((act == NULL || strcmp(act, "hostdev") == 0) &&
+ if ((act == NULL || strcmp(act, "host") == 0) &&
!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
@@ -290,12 +310,46 @@ int misc_init_r(void)
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
- /* clear resets */
+ /*
+ * Take USB out of reset:
+ * -Initial status = all cores are in reset
+ * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
+ * -wait 1 ms
+ * -deassert reset to PHY
+ * -wait 1 ms
+ * -deassert reset to HOST
+ * -wait 4 ms
+ * -deassert all other resets
+ */
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
+ SDR0_SRST1_P4OPB0 | \
+ SDR0_SRST1_OPBA2 | \
+ SDR0_SRST1_PLB42OPB1 | \
+ SDR0_SRST1_OPB2PLB40);
+ mtsdr(SDR0_SRST1, sdr0_srst1);
+ udelay(1000);
+
+ mfsdr(SDR0_SRST1, sdr0_srst1);
+ sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
+ mtsdr(SDR0_SRST1, sdr0_srst1);
udelay(1000);
+
+ mfsdr(SDR0_SRST0, sdr0_srst0);
+ sdr0_srst0 &= ~SDR0_SRST0_USB2H;
+ mtsdr(SDR0_SRST0, sdr0_srst0);
+ udelay(4000);
+
+ /* finally all the other resets */
mtsdr(SDR0_SRST1, 0x00000000);
- udelay(1000);
mtsdr(SDR0_SRST0, 0x00000000);
+ if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
+ /* enable power on USB socket */
+ out_be32((void*)GPIO1_OR,
+ in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
+ }
+
printf("USB: Host\n");
} else if ((strcmp(act, "dev") == 0) ||
@@ -498,7 +552,7 @@ int pci_pre_init(struct pci_controller *hose)
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
char *ptmla_str, *ptmms_str;
@@ -516,8 +570,8 @@ void pci_target_init(struct pci_controller *hose)
*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
/* - disabled b4 setting */
- out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+ out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
+ out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
/* and enable region */
@@ -547,14 +601,14 @@ void pci_target_init(struct pci_controller *hose)
out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16));
out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16));
} else {
- /* BAR2: default: 16 MB FPGA + registers */
- out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */
+ /* BAR2: default: 4MB FPGA */
+ out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
}
if (is_monarch()) {
/* BAR2: map FPGA registers behind system memory at 1GB */
- pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008);
+ pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
}
/*
@@ -562,8 +616,8 @@ void pci_target_init(struct pci_controller *hose)
*/
/* Program the board's vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CFG_PCI_SUBSYS_VENDORID);
+ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_VENDOR_ID,
+ CONFIG_SYS_PCI_SUBSYS_VENDORID);
/* disabled for PMC405 backward compatibility */
/* Configure command register as bus master */
@@ -571,19 +625,19 @@ void pci_target_init(struct pci_controller *hose)
/* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
+ pci_hose_write_config_word(hose, 0, PCI_LATENCY_TIMER, 1);
/* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
+ pci_hose_write_config_word(hose, 0, PCI_ERREN, 0);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
if (!is_monarch()) {
/* Program the board's subsystem id/classcode */
- pci_write_config_word(0, PCI_SUBSYSTEM_ID,
- CFG_PCI_SUBSYS_ID_NONMONARCH);
- pci_write_config_word(0, PCI_CLASS_SUB_CODE,
- CFG_PCI_CLASSCODE_NONMONARCH);
+ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
+ CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
+ pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
+ CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
/* PCI configuration done: release ERREADY */
out_be32((void*)GPIO1_OR,
@@ -592,18 +646,21 @@ void pci_target_init(struct pci_controller *hose)
in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
} else {
/* Program the board's subsystem id/classcode */
- pci_write_config_word(0, PCI_SUBSYSTEM_ID,
- CFG_PCI_SUBSYS_ID_MONARCH);
- pci_write_config_word(0, PCI_CLASS_SUB_CODE,
- CFG_PCI_CLASSCODE_MONARCH);
+ pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
+ CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
+ pci_hose_write_config_word(hose, 0, PCI_CLASS_SUB_CODE,
+ CONFIG_SYS_PCI_CLASSCODE_MONARCH);
}
+
+ /* enable host configuration */
+ pci_hose_write_config_dword(hose, 0, PCI_BRDGOPT2, 0x00000101);
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
/*
* pci_master_init
*/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
@@ -620,12 +677,18 @@ void pci_master_init(struct pci_controller *hose)
PCI_COMMAND_MEMORY);
}
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
static void wait_for_pci_ready(void)
{
int i;
char *s = getenv("pcidelay");
+ /*
+ * We have our own handling of the pcidelay variable.
+ * Using CONFIG_PCI_BOOTDELAY enables pausing for host
+ * and adapter devices. For adapter devices we do not
+ * want this.
+ */
if (s) {
int ms = simple_strtoul(s, NULL, 10);
printf("PCI: Waiting for %d ms\n", ms);
@@ -692,23 +755,37 @@ int post_hotkeys_pressed(void)
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
+ char *s;
+ unsigned short val_method, val_behavior;
+
+ /* special LED setup for NGCC/CANDES */
+ if ((s = getenv("bd_type")) &&
+ ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
+ val_method = 0x0e0a;
+ val_behavior = 0x0cf2;
+ } else {
+ /* PMC440 standard type */
+ val_method = 0x0e10;
+ val_behavior = 0x0cf0;
+ }
+
if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
- miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0);
- miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10);
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
+ miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
}
if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
- miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0);
- miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10);
+ miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
+ miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
}
}
#endif
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
/*
* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
@@ -720,8 +797,8 @@ void reset_phy(void)
*/
int eeprom_write_enable(unsigned dev_addr, int state)
{
- if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
- (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
+ if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
+ (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
return -1;
} else {
switch (state) {
@@ -743,9 +820,9 @@ int eeprom_write_enable(unsigned dev_addr, int state)
}
return state;
}
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
-#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
uchar *buffer, unsigned cnt)
{
@@ -753,7 +830,7 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
unsigned blk_off;
int rcode = 0;
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
eeprom_write_enable(dev_addr, 1);
#endif
/*
@@ -776,7 +853,7 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
len = end - offset;
-#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
maxlen = BOOT_EEPROM_PAGE_SIZE -
@@ -793,11 +870,11 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
buffer += len;
offset += len;
-#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
- udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+ udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
}
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
eeprom_write_enable(dev_addr, 0);
#endif
return rcode;
@@ -845,13 +922,13 @@ int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
return rcode;
}
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
int usb_board_init(void)
{
char *act = getenv("usbact");
int i;
- if ((act == NULL || strcmp(act, "hostdev") == 0) &&
+ if ((act == NULL || strcmp(act, "host") == 0) &&
!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
/* enable power on USB socket */
out_be32((void*)GPIO1_OR,
@@ -875,4 +952,25 @@ int usb_board_init_fail(void)
usb_board_stop();
return 0;
}
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ int rc;
+
+ __ft_board_setup(blob, bd);
+
+ /*
+ * Disable PCI in non-monarch mode.
+ */
+ if (!is_monarch()) {
+ rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
+ "disabled", sizeof("disabled"), 1);
+ if (rc) {
+ printf("Unable to update property status in PCI node, err=%s\n",
+ fdt_strerror(rc));
+ }
+ }
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h
index 7e70fd1..295cec1 100644
--- a/board/esd/pmc440/pmc440.h
+++ b/board/esd/pmc440/pmc440.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
*
* See file CREDITS for list of people who contributed to this
@@ -24,8 +24,7 @@
#ifndef __PMC440_H__
#define __PMC440_H__
-
-/*-----------------------------------------------------------------------
+/*
* GPIOs
*/
#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */
@@ -41,9 +40,10 @@
#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */
#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */
#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */
-#define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */
-/* FPGA programming pin configuration */
+/*
+ * FPGA programming pin configuration
+ */
#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */
#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */
@@ -51,10 +51,10 @@
#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */
#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */
-/*-----------------------------------------------------------------------
+/*
* FPGA interface
*/
-#define FPGA_BA CFG_FPGA_BASE0
+#define FPGA_BA CONFIG_SYS_FPGA_BASE0
#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
#define FPGA_IN32(p) in_be32((void*)(p))
#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
@@ -103,7 +103,6 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
#define RESET_OUT (1 << 19)
#define IRIGB_R_OUT (1 << 14)
-
/* status register */
#define STATUS_VERSION_SHIFT 24
#define STATUS_VERSION_MASK 0xff000000
@@ -115,13 +114,11 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
#define STATUS_FIFO_ISF (1 << 9)
#define STATUS_HOST_ISF (1 << 8)
-
/* inputs */
#define RESET_IN (1 << 0)
#define CLOCK_IN (1 << 1)
#define IRIGB_R_IN (1 << 5)
-
/* hostctrl register */
#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17)
#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16)
@@ -134,10 +131,10 @@ typedef struct pmc440_fpga_s pmc440_fpga_t;
#define HOSTCTRL_HCINT_GATE (1 << 1)
#define HOSTCTRL_HCINT_FLAG (1 << 0)
-#define NGCC_CTRL_BASE (CFG_FPGA_BASE0 + 0x80000)
+#define NGCC_CTRL_BASE (CONFIG_SYS_FPGA_BASE0 + 0x80000)
#define NGCC_CTRL_FPGARST_N (1 << 2)
-/*-----------------------------------------------------------------------
+/*
* FPGA to PPC interrupt
*/
#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */
diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c
index c7294c9..197857a 100644
--- a/board/esd/pmc440/sdram.c
+++ b/board/esd/pmc440/sdram.c
@@ -111,5 +111,5 @@ phys_size_t initdram (int board_type)
*/
set_mcsr(get_mcsr());
- return (CFG_MBYTES_SDRAM << 20);
+ return (CONFIG_SYS_MBYTES_SDRAM << 20);
}
diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds
index ae2e18d..6e1e169 100644
--- a/board/esd/pmc440/u-boot-nand.lds
+++ b/board/esd/pmc440/u-boot-nand.lds
@@ -57,7 +57,7 @@ SECTIONS
/* Align to next NAND block */
. = ALIGN(0x4000);
- common/environment.o (.ppcenv)
+ common/env_embedded.o (.ppcenv)
/* Keep some space here for redundant env and potential bad env blocks */
. = ALIGN(0x10000);
@@ -129,6 +129,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
diff --git a/board/esd/pmc440/u-boot.lds b/board/esd/pmc440/u-boot.lds
index b20fb1c..05152b7 100644
--- a/board/esd/pmc440/u-boot.lds
+++ b/board/esd/pmc440/u-boot.lds
@@ -135,9 +135,10 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
- ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+ ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/tasreg/flash.c b/board/esd/tasreg/flash.c
index 13c07d2..ce905e9 100644
--- a/board/esd/tasreg/flash.c
+++ b/board/esd/tasreg/flash.c
@@ -45,13 +45,13 @@ unsigned long flash_init (void)
int i;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
- size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+ size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -65,8 +65,8 @@ unsigned long flash_init (void)
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_FLASH_BASE,
- CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ CONFIG_SYS_FLASH_BASE,
+ CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-1,
&flash_info[0]);
flash_info[0].size = size_b0;
diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c
index fabb746..64e6d63 100644
--- a/board/esd/tasreg/tasreg.c
+++ b/board/esd/tasreg/tasreg.c
@@ -40,8 +40,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
/* predefine these here for FPGA programming (before including fpga.c) */
#define SET_FPGA(data) mbar2_writeLong(MCFSIM_GPIO1_OUT, data)
-#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_DONE)
-#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_INIT)
+#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_INIT)
#define FPGA_PROG_ACTIVE_HIGH /* on this platform is PROG active high! */
#define out32(a,b) /* nothing to do (gpio already configured) */
@@ -70,7 +70,7 @@ int checkboard (void) {
/*
* Set LED on
*/
- val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED;
+ val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
mbar2_writeLong(MCFSIM_GPIO1_OUT, val); /* Set LED on */
return 0;
@@ -85,13 +85,13 @@ phys_size_t initdram (int board_type) {
* RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
*/
-#ifdef CFG_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
/*
* Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
*/
mbar_writeShort(MCFSIM_DCR, 0x8239);
-#elif CFG_PLL_BYPASS
+#elif CONFIG_SYS_PLL_BYPASS
/*
* Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
* SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
@@ -129,7 +129,7 @@ phys_size_t initdram (int board_type) {
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
@@ -150,8 +150,8 @@ int misc_init_r (void)
int i;
uchar buf[8];
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds
index afdb720..aec7e9b 100644
--- a/board/esd/tasreg/u-boot.lds
+++ b/board/esd/tasreg/u-boot.lds
@@ -62,7 +62,7 @@ SECTIONS
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.text)
+ common/env_embedded.o (.text)
*(.text)
*(.fixup)
diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/voh405/flash.c
+++ b/board/esd/voh405/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -91,7 +91,7 @@ unsigned long flash_init (void)
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
diff --git a/board/esd/voh405/u-boot.lds b/board/esd/voh405/u-boot.lds
index d70d379..d8fbea3 100644
--- a/board/esd/voh405/u-boot.lds
+++ b/board/esd/voh405/u-boot.lds
@@ -66,14 +66,14 @@ SECTIONS
cpu/ppc4xx/4xx_uart.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/4xx_enet.o (.text)
+ drivers/net/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -144,6 +144,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
index 5253422..ec65ffd 100644
--- a/board/esd/voh405/voh405.c
+++ b/board/esd/voh405/voh405.c
@@ -104,21 +104,14 @@ int board_early_init_f (void)
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
unsigned short *lcd_contrast =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
unsigned short *lcd_backlight =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
@@ -126,8 +119,8 @@ int misc_init_r (void)
int i;
char *str;
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
@@ -190,22 +183,22 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
udelay(10); /* wait 10us */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
/*
* Set NAND-FLASH GPIO signals to default
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
/*
* Setup EEPROM write protection
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
/*
* Enable interrupts in exar duart mcr[3]
@@ -219,29 +212,29 @@ int misc_init_r (void)
str = getenv("bd_type");
if (strcmp(str, "voh405_bw") == 0) {
lcd_setup(0, 1);
- lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13704_320_240_4bpp,
sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
} else if (strcmp(str, "voh405_bwbw") == 0) {
lcd_setup(0, 1);
- lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13704_320_240_4bpp,
sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
lcd_setup(1, 1);
- lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_320_240_4bpp,
sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
} else if (strcmp(str, "voh405_bwc") == 0) {
lcd_setup(0, 1);
- lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
regs_13704_320_240_4bpp,
sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
logo_bmp_320, sizeof(logo_bmp_320));
lcd_setup(1, 0);
- lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+ lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
regs_13806_640_480_16bpp,
sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
logo_bmp_640, sizeof(logo_bmp_640));
@@ -253,8 +246,8 @@ int misc_init_r (void)
/*
* Set invert bit in small lcd controller
*/
- out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2),
- in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01);
+ out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
+ in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
/*
* Set default contrast voltage on epson vga controller
@@ -269,7 +262,7 @@ int misc_init_r (void)
/*
* Enable external I2C bus
*/
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
return (0);
}
@@ -303,48 +296,19 @@ int checkboard (void)
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
volatile unsigned short *fpga_mode =
- (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) { /* assert RESET */
- *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+ *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET);
} else { /* release RESET */
- *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+ *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET;
}
}
#endif /* CONFIG_IDE_RESET */
@@ -362,7 +326,7 @@ void reset_phy(void)
}
#endif
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
* 0: disable write
@@ -373,23 +337,23 @@ void reset_phy(void)
*/
int eeprom_write_enable (unsigned dev_addr, int state)
{
- if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
return -1;
} else {
switch (state) {
case 1:
/* Enable write access, clear bit GPIO0. */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO0. */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
+ state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
break;
}
}
@@ -403,21 +367,21 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (query) {
/* Query write access state. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
if (state < 0) {
puts ("Query of write access state failed.\n");
} else {
printf ("Write access for device 0x%0x is %sabled.\n",
- CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
state = 0;
}
} else {
if ('0' == argv[1][0]) {
/* Disable write access. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
} else {
/* Enable write access. */
- state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
}
if (state < 0) {
puts ("Setup of write access state failed.\n");
@@ -430,4 +394,4 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
"eepwren - Enable / disable / query EEPROM write access\n",
NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/vom405/flash.c
+++ b/board/esd/vom405/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -91,7 +91,7 @@ unsigned long flash_init (void)
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
diff --git a/board/esd/vom405/u-boot.lds b/board/esd/vom405/u-boot.lds
index 21547ac..c9472f9 100644
--- a/board/esd/vom405/u-boot.lds
+++ b/board/esd/vom405/u-boot.lds
@@ -61,18 +61,6 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
@@ -143,6 +131,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c
index af8efcf..1b1479f 100644
--- a/board/esd/vom405/vom405.c
+++ b/board/esd/vom405/vom405.c
@@ -37,7 +37,6 @@ const unsigned char fpgadata[] =
};
int filesize = sizeof(fpgadata);
-
int board_early_init_f (void)
{
/*
@@ -76,9 +75,6 @@ int board_early_init_f (void)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
int misc_init_r (void)
{
/* adjust flash start and offset */
@@ -88,11 +84,9 @@ int misc_init_r (void)
return (0);
}
-
/*
* Check Board Identity:
*/
-
int checkboard (void)
{
char str[64];
@@ -127,25 +121,6 @@ int checkboard (void)
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/wuh405/flash.c
+++ b/board/esd/wuh405/flash.c
@@ -48,7 +48,7 @@ unsigned long flash_init (void)
int size_val = 0;
/* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
@@ -91,7 +91,7 @@ unsigned long flash_init (void)
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
diff --git a/board/esd/wuh405/u-boot.lds b/board/esd/wuh405/u-boot.lds
index 644174a..e2e2512 100644
--- a/board/esd/wuh405/u-boot.lds
+++ b/board/esd/wuh405/u-boot.lds
@@ -72,7 +72,7 @@ SECTIONS
lib_generic/zlib.o (.text)
/* . = env_offset;*/
-/* common/environment.o(.text)*/
+/* common/env_embedded.o(.text)*/
*(.text)
*(.fixup)
@@ -142,6 +142,7 @@ SECTIONS
*(.dynbss)
*(.bss)
*(COMMON)
+ . = ALIGN(4);
}
_end = . ;
PROVIDE (end = .);
diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c
index 0590fc7..5eca3bd 100644
--- a/board/esd/wuh405/wuh405.c
+++ b/board/esd/wuh405/wuh405.c
@@ -80,15 +80,6 @@ int board_early_init_f (void)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
@@ -101,8 +92,8 @@ int misc_init_r (void)
int index;
int i;
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
@@ -164,9 +155,9 @@ int misc_init_r (void)
/*
* Reset external DUARTs
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
udelay(10); /* wait 10us */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
/*
@@ -202,15 +193,3 @@ int checkboard (void)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}