diff options
Diffstat (limited to 'board/esd/pmc440')
-rw-r--r-- | board/esd/pmc440/cmd_pmc440.c | 10 | ||||
-rw-r--r-- | board/esd/pmc440/init.S | 11 | ||||
-rw-r--r-- | board/esd/pmc440/pmc440.c | 32 | ||||
-rw-r--r-- | board/esd/pmc440/sdram.c | 82 |
4 files changed, 82 insertions, 53 deletions
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 1af431b..476e940 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -497,15 +497,15 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* map PCI address at 0xc0000000 in PLB space */ /* PMM1 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1MA, 0x00000000); + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM1 Local Address */ - out32r(PCIX0_PMM1LA, 0xc0000000); + out32r(PCIL0_PMM1LA, 0xc0000000); /* PMM1 PCI Low Address */ - out32r(PCIX0_PMM1PCILA, pciaddr); + out32r(PCIL0_PMM1PCILA, pciaddr); /* PMM1 PCI High Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* 256MB + No prefetching, and enable region */ - out32r(PCIX0_PMM1MA, 0xf0000001); + out32r(PCIL0_PMM1MA, 0xf0000001); } else { printf("Usage:\npmm %s\n", cmdtp->help); } diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S index 26a8282..6585fed 100644 --- a/board/esd/pmc440/init.S +++ b/board/esd/pmc440/init.S @@ -23,7 +23,7 @@ #include <asm-ppc/mmu.h> #include <config.h> -/************************************************************************** +/* * TLB TABLE * * This table is used by the cpu boot code to setup the initial tlb @@ -32,7 +32,7 @@ * * Pointer to the table is returned in r1 * - *************************************************************************/ + */ .section .bootpg,"ax" .globl tlbtab @@ -49,12 +49,7 @@ tlbtab: tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) #endif - /* TLB-entry for DDR SDRAM (Up to 2GB) */ -#ifdef CONFIG_4xx_DCACHE - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) -#else - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) -#endif + /* TLB entries for DDR2 SDRAM are generated dynamically */ #ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index f0f9bff..ec92552 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -208,7 +208,7 @@ int misc_init_f(void) if (getenv("pciearly") && (!is_monarch())) { printf("PCI: early target init\n"); - pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA); + pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA); pci_target_init(&hose); } return 0; @@ -568,42 +568,42 @@ void pci_target_init(struct pci_controller *hose) * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ /* and enable region */ if (!is_monarch()) { ptmla_str = getenv("ptm1la"); ptmms_str = getenv("ptm1ms"); if(NULL != ptmla_str && NULL != ptmms_str ) { - out32r(PCIX0_PTM1MS, + out32r(PCIL0_PTM1MS, simple_strtoul(ptmms_str, NULL, 16)); - out32r(PCIX0_PTM1LA, + out32r(PCIL0_PTM1LA, simple_strtoul(ptmla_str, NULL, 16)); } else { /* BAR1: default top 64MB of RAM */ - out32r(PCIX0_PTM1MS, 0xfc000001); - out32r(PCIX0_PTM1LA, 0x0c000000); + out32r(PCIL0_PTM1MS, 0xfc000001); + out32r(PCIL0_PTM1LA, 0x0c000000); } } else { /* BAR1: default: complete 256MB RAM */ - out32r(PCIX0_PTM1MS, 0xf0000001); - out32r(PCIX0_PTM1LA, 0x00000000); + out32r(PCIL0_PTM1MS, 0xf0000001); + out32r(PCIL0_PTM1LA, 0x00000000); } ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */ ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */ if(NULL != ptmla_str && NULL != ptmms_str ) { - out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16)); - out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16)); + out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16)); + out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16)); } else { /* BAR2: default: 4MB FPGA */ - out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */ } if (is_monarch()) { diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c index bb46ecc..c3528bc 100644 --- a/board/esd/pmc440/sdram.c +++ b/board/esd/pmc440/sdram.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2009 + * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu + * * (C) Copyright 2006 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com @@ -31,33 +34,30 @@ #include <common.h> #include <asm/processor.h> #include <asm/io.h> +#include <asm/mmu.h> #include <ppc440.h> extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); +struct sdram_conf_s { + ulong size; + int rows; + int banks; +}; -#if defined(CONFIG_NAND_SPL) -/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big - * for the 4k NAND boot image so define bus_frequency to 133MHz here - * which is save for the refresh counter setup. - */ -#define get_bus_freq(val) 133000000 -#endif +struct sdram_conf_s sdram_conf[] = { + {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */ + {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */ + {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */ +}; -/************************************************************************* - * +/* * initdram -- 440EPx's DDR controller is a DENALI Core - * - ************************************************************************/ -phys_size_t initdram (int board_type) + */ +int initdram_by_rb(int rows, int banks) { -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -#if !defined(CONFIG_NAND_SPL) ulong speed = get_bus_freq(0); -#else - ulong speed = 133333333; /* 133MHz is on the safe side */ -#endif mtsdram(DDR0_02, 0x00000000); @@ -89,21 +89,25 @@ phys_size_t initdram (int board_type) mtsdram(DDR0_27, 0x0000682B); mtsdram(DDR0_28, 0x00000000); mtsdram(DDR0_31, 0x00000000); - mtsdram(DDR0_42, 0x01000006); - mtsdram(DDR0_43, 0x030A0200); + + mtsdram(DDR0_42, + DDR0_42_ADDR_PINS_DECODE(14 - rows) | + 0x00000006); + mtsdram(DDR0_43, + DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) | + 0x030A0200); + mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); denali_wait_for_dlllock(); -#endif /* #ifndef CONFIG_NAND_U_BOOT */ #ifdef CONFIG_DDR_DATA_EYE - /* -----------------------------------------------------------+ + /* * Perform data eye search if requested. - * ----------------------------------------------------------*/ + */ denali_core_search_data_eye(); #endif - /* * Clear possible errors resulting from data-eye-search. * If not done, then we could get an interrupt later on when @@ -111,5 +115,35 @@ phys_size_t initdram (int board_type) */ set_mcsr(get_mcsr()); - return (CONFIG_SYS_MBYTES_SDRAM << 20); + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t size; + int n; + + /* go through supported memory configurations */ + for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) { + size = sdram_conf[n].size; + + /* program TLB entries */ + program_tlb(0, CONFIG_SYS_SDRAM_BASE, size, + TLB_WORD2_I_ENABLE); + + /* + * setup denali core + */ + initdram_by_rb(sdram_conf[n].rows, + sdram_conf[n].banks); + + /* check for suitable configuration */ + if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size) + return size; + + /* delete TLB entries */ + remove_tlb(CONFIG_SYS_SDRAM_BASE, size); + } + + return 0; } |