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-rw-r--r--board/esd/pf5200/flash.c32
-rw-r--r--board/esd/pf5200/pf5200.c24
2 files changed, 31 insertions, 25 deletions
diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c
index 53afbc0..9850445 100644
--- a/board/esd/pf5200/flash.c
+++ b/board/esd/pf5200/flash.c
@@ -23,7 +23,7 @@
#include <common.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
typedef unsigned short FLASH_PORT_WIDTH;
typedef volatile unsigned short FLASH_PORT_WIDTHV;
@@ -60,7 +60,7 @@ unsigned long flash_init(void)
extern void flash_preinit(void);
extern void flash_afterinit(uint, ulong, ulong);
- ulong flashbase = CFG_FLASH_BASE;
+ ulong flashbase = CONFIG_SYS_FLASH_BASE;
flash_preinit();
@@ -69,18 +69,18 @@ unsigned long flash_init(void)
flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
size += flash_info[i].size;
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
- CFG_MONITOR_BASE + monitor_flash_len - 1,
- flash_get_info(CFG_MONITOR_BASE));
+ flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ flash_get_info(CONFIG_SYS_MONITOR_BASE));
#endif
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
- CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
- flash_get_info(CFG_ENV_ADDR));
+ flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
+ flash_get_info(CONFIG_ENV_ADDR));
#endif
flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
@@ -107,14 +107,14 @@ static flash_info_t *flash_get_info(ulong base) {
int i;
flash_info_t *info;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
info = &flash_info[i];
if ((info->size) && (info->start[0] <= base)
&& (base <= info->start[0] + info->size - 1)) {
break;
}
}
- return (i == CFG_MAX_FLASH_BANKS ? 0 : info);
+ return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
}
/*-----------------------------------------------------------------------
@@ -336,7 +336,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) {
udelay(1000);
while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
if (intel) {
/* suspend erase */
@@ -347,14 +347,14 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) {
break;
}
/* show that we're waiting */
- if ((get_timer(last)) > CFG_HZ) {
+ if ((get_timer(last)) > CONFIG_SYS_HZ) {
/* every second */
putc('.');
last = get_timer(0);
}
}
/* show that we're waiting */
- if ((get_timer(last)) > CFG_HZ) {
+ if ((get_timer(last)) > CONFIG_SYS_HZ) {
/* every second */
putc('.');
last = get_timer(0);
@@ -452,7 +452,7 @@ static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data) {
/* data polling for D7 */
while (res == 0
&& (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW) 0x00F000F0; /* reset bank */
res = 1;
}
diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c
index 7970f89..f7962af 100644
--- a/board/esd/pf5200/pf5200.c
+++ b/board/esd/pf5200/pf5200.c
@@ -32,6 +32,7 @@
#include <mpc5xxx.h>
#include <pci.h>
#include <command.h>
+#include <netdev.h>
#include "mt46v16m16-75.h"
@@ -80,7 +81,7 @@ static void sdram_start(int hi_addr)
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
@@ -105,9 +106,9 @@ phys_size_t initdram(int board_type)
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+ test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
sdram_start(1);
- test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+ test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (test1 > test2) {
sdram_start(0);
@@ -143,9 +144,9 @@ phys_size_t initdram(int board_type)
#if 0
/* find RAM size using SDRAM CS1 only */
sdram_start(0);
- get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(1);
- get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+ get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
sdram_start(0);
#endif
/* set SDRAM CS1 size according to the amount of RAM found */
@@ -179,10 +180,10 @@ void flash_afterinit(ulong size)
/* adjust mapping */
*(vu_long *) MPC5XXX_BOOTCS_START =
*(vu_long *) MPC5XXX_CS0_START =
- START_REG(CFG_BOOTCS_START | size);
+ START_REG(CONFIG_SYS_BOOTCS_START | size);
*(vu_long *) MPC5XXX_BOOTCS_STOP =
*(vu_long *) MPC5XXX_CS0_STOP =
- STOP_REG(CFG_BOOTCS_START | size, size);
+ STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
}
}
@@ -257,13 +258,18 @@ void init_power_switch(void)
*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
__asm__ volatile ("sync");
}
- *(vu_char *) CFG_CS1_START = 0x02; /* Red Power LED on */
+ *(vu_char *) CONFIG_SYS_CS1_START = 0x02; /* Red Power LED on */
__asm__ volatile ("sync");
- *(vu_char *) (CFG_CS1_START + 1) = 0x02; /* Disable driver for KB11 */
+ *(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02; /* Disable driver for KB11 */
__asm__ volatile ("sync");
}
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
void power_set_reset(int power)
{
debug("ide_set_reset(%d)\n", power);
generated by cgit v1.1 at 2024-11-24 08:46:36 +0000