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Diffstat (limited to 'board/esd/pci405')
-rw-r--r--board/esd/pci405/Kconfig12
-rw-r--r--board/esd/pci405/MAINTAINERS6
-rw-r--r--board/esd/pci405/Makefile9
-rw-r--r--board/esd/pci405/cmd_pci405.c97
-rw-r--r--board/esd/pci405/flash.c85
-rw-r--r--board/esd/pci405/fpgadata.c1492
-rw-r--r--board/esd/pci405/pci405.c366
-rw-r--r--board/esd/pci405/pci405.h16
-rw-r--r--board/esd/pci405/writeibm.S205
9 files changed, 0 insertions, 2288 deletions
diff --git a/board/esd/pci405/Kconfig b/board/esd/pci405/Kconfig
deleted file mode 100644
index 0a6524d..0000000
--- a/board/esd/pci405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_PCI405
-
-config SYS_BOARD
- default "pci405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "PCI405"
-
-endif
diff --git a/board/esd/pci405/MAINTAINERS b/board/esd/pci405/MAINTAINERS
deleted file mode 100644
index cf9c1c9..0000000
--- a/board/esd/pci405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-PCI405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/pci405/
-F: include/configs/PCI405.h
-F: configs/PCI405_defconfig
diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile
deleted file mode 100644
index 9e659c7..0000000
--- a/board/esd/pci405/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pci405.o flash.o ../common/misc.o cmd_pci405.o
-obj-y += writeibm.o
diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c
deleted file mode 100644
index 29c688a..0000000
--- a/board/esd/pci405/cmd_pci405.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * (C) Copyright 2002-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <asm/4xx_pci.h>
-#include <asm/processor.h>
-
-#include "pci405.h"
-
-#if defined(CONFIG_CMD_BSP)
-
-/*
- * Command loadpci: wait for signal from host and boot image.
- */
-int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int *ptr;
- int count = 0;
- int count2 = 0;
- int i;
- char addr[16];
- char str[] = "\\|/-";
- char *local_args[2];
-
- /*
- * Mark sync address
- */
- ptr = 0;
- /* cppcheck-suppress nullPointer */
- *ptr = 0xffffffff;
- puts("\nWaiting for image from pci host -");
-
- /*
- * Wait for host to write the start address
- */
- /* cppcheck-suppress nullPointer */
- while (*ptr == 0xffffffff) {
- count++;
- if (!(count % 100)) {
- count2++;
- putc(0x08); /* backspace */
- putc(str[count2 % 4]);
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- puts("\nAbort\n");
- return 0;
- }
-
- udelay(1000);
- }
-
- if (*ptr == PCI_RECONFIG_MAGIC) {
- /*
- * Save own pci configuration in PRAM
- */
- memset((char *)PCI_REGS_ADDR, 0, PCI_REGS_LEN);
- ptr = (unsigned int *)PCI_REGS_ADDR + 1;
- for (i=0; i<0x40; i+=4) {
- pci_read_config_dword(PCIDEVID_405GP, i, ptr++);
- }
- ptr = (unsigned int *)PCI_REGS_ADDR;
- *ptr = crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4);
-
- printf("\nStoring PCI Configuration Regs...\n");
- } else {
- sprintf(addr, "%08x", *ptr);
-
- /*
- * Boot image via bootm
- */
- printf("\nBooting Image at addr 0x%s ...\n", addr);
- setenv("loadaddr", addr);
-
- local_args[0] = argv[0];
- local_args[1] = NULL;
- do_bootm (cmdtp, 0, 1, local_args);
- }
-
- return 0;
-}
-U_BOOT_CMD(
- loadpci, 1, 1, do_loadpci,
- "Wait for pci-image and boot it",
- ""
-);
-#endif
diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c
deleted file mode 100644
index 113111d..0000000
--- a/board/esd/pci405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -monitor_flash_len,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/pci405/fpgadata.c b/board/esd/pci405/fpgadata.c
deleted file mode 100644
index d145826..0000000
--- a/board/esd/pci405/fpgadata.c
+++ /dev/null
@@ -1,1492 +0,0 @@
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-0x5d, 0xdb, 0xce, 0x56, 0x77, 0x4d, 0x4b, 0xeb,
-0x4f, 0x86, 0x15, 0xb4, 0x87, 0x76, 0x42, 0xa7,
-0x32, 0x57, 0x2a, 0x68, 0x23, 0x5a, 0xa1, 0xb4,
-0xd7, 0x6c, 0xa7, 0xf5, 0x73, 0x12, 0x99, 0xac,
-0x7b, 0x5e, 0xfb, 0x7e, 0x66, 0x9d, 0xc4, 0xfe,
-0x3e, 0xda, 0x40, 0xee, 0xfd, 0x06, 0xe0, 0x7b,
-0x50, 0xda, 0x6b, 0x5a, 0x8c, 0xfe, 0x27, 0x34,
-0x14, 0x52, 0xaa, 0x1a, 0x05, 0xc9, 0xea, 0x0b,
-0x11, 0x58, 0x0c, 0x96, 0x7d, 0x6f, 0x6d, 0x14,
-0xec, 0x93, 0xab, 0x3d, 0x06, 0x72, 0xcf, 0xb3,
-0xff, 0xd1, 0x33, 0x89, 0xf2, 0x41, 0x18, 0xc8,
-0xfd, 0x4b, 0x2f, 0x18, 0xbe, 0xf6, 0xbf, 0x76,
-0xd5, 0xd5, 0x5d, 0xfb, 0x33, 0xb7, 0xfb, 0xdf,
-0x6c, 0xf6, 0x1f, 0xb8, 0xea, 0x27, 0x26, 0x26,
-0xd4, 0x49, 0x85, 0xff, 0x37, 0xeb, 0x72, 0x36,
-0x2f, 0x91, 0xff, 0xf3, 0x36, 0xff, 0x49, 0xed,
-0xa6, 0xda, 0xae, 0x35, 0xb7, 0xff, 0x97, 0x6c,
-0xde, 0x6e, 0xd7, 0xd6, 0x26, 0xfc, 0xbf, 0x6c,
-0xf3, 0x80, 0xa6, 0xae, 0xbd, 0xdf, 0x54, 0x9b,
-0xff, 0x17, 0xdb, 0xc1, 0x27, 0xbc, 0x9f, 0xed,
-0xfa, 0x17, 0xde, 0x1c, 0x98, 0xcd, 0xc3, 0x35,
-0xd7, 0xa7, 0x36, 0xff, 0x1f, 0xa8, 0xfb, 0x97,
-0x2f, 0xf6, 0xb7, 0x1c, 0x89, 0xf6, 0xff, 0x45,
-0xbf, 0xfd, 0xf7, 0xb6, 0xf9, 0xf4, 0xfa, 0xf4,
-0xfa, 0xf4, 0xfa, 0xf4, 0xfa, 0xf4, 0xfa, 0xf4,
-0xfa, 0xff, 0xe5, 0xd2, 0xf6, 0x49, 0xa2, 0xed,
-0x93, 0xea, 0x7f, 0x76, 0x5f, 0x3e, 0xbd, 0x3e,
-0xbd, 0x3e, 0xbd, 0x3e, 0xbd, 0x3e, 0xbd, 0x3e,
-0xbd, 0xfe, 0x33, 0xae, 0x20, 0xfb, 0x73, 0x09,
-0x50, 0xf9, 0x6b, 0xe3, 0xef, 0xff, 0xf3, 0x41,
-0x50, 0xa6, 0xfd, 0xeb, 0xbf, 0xaf, 0xfd, 0x9e,
-0x23, 0x08, 0x69, 0xce, 0x6a, 0xbf, 0x3b, 0x35,
-0xb5, 0xaf, 0xff, 0x13, 0x87, 0x7b, 0xf6, 0xdd,
-0xd4, 0x60, 0x00, 0x00,
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
deleted file mode 100644
index 566f6f7..0000000
--- a/board/esd/pci405/pci405.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <malloc.h>
-#include <pci.h>
-#include <asm/4xx_pci.h>
-#include <asm/io.h>
-
-#include "pci405.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Prototypes */
-unsigned long fpga_done_state(void);
-unsigned long fpga_init_state(void);
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* predefine these here */
-#define FPGA_DONE_STATE (fpga_done_state())
-#define FPGA_INIT_STATE (fpga_init_state())
-
-/* fpga configuration data - generated by bin2cc */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
-#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
-
-#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
-#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
-
-
-int board_revision(void)
-{
- unsigned long CPC0_CR0Reg;
- unsigned long value;
-
- /*
- * Get version of PCI405 board from GPIO's
- */
-
- /*
- * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
- out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
- udelay(1000); /* wait some time before reading input */
- value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
-
- /*
- * Restore GPIO settings
- */
- mtdcr(CPC0_CR0, CPC0_CR0Reg);
-
- switch (value) {
- case 0x00100200:
- /* CS2==1 && IRQ5==1 -> version 1.0 and 1.1 */
- return 1;
- case 0x00000200:
- /* CS2==0 && IRQ5==1 -> version 1.2 */
- return 2;
- case 0x00000000:
- /* CS2==0 && IRQ5==0 -> version 1.3 */
- return 3;
-#if 0 /* not yet manufactured ! */
- case 0x00100000:
- /* CS2==1 && IRQ5==0 -> version 1.4 */
- return 4;
-#endif
- default:
- /* should not be reached! */
- return 0;
- }
-}
-
-
-unsigned long fpga_done_state(void)
-{
- if (gd->board_type < 2) {
- return FPGA_DONE_STATE_V11;
- } else {
- return FPGA_DONE_STATE_V12;
- }
-}
-
-
-unsigned long fpga_init_state(void)
-{
- if (gd->board_type < 2) {
- return FPGA_INIT_STATE_V11;
- } else {
- return FPGA_INIT_STATE_V12;
- }
-}
-
-
-int board_early_init_f (void)
-{
- unsigned long CPC0_CR0Reg;
-
- /*
- * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
- */
- out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
- out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
- out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
- out_be32((void*)GPIO0_OR, 0); /* pull prg low */
-
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) CAN2; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) CAN3; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) unused; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
-
- /*
- * Setup GPIO pins (CS6+CS7 as GPIO)
- */
- mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
- unsigned int *ptr;
- unsigned int *magic;
-
- /*
- * On PCI-405 the environment is saved in eeprom!
- * FPGA can be gzip compressed (malloc) and booted this late.
- */
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc ('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
-
- /*
- * Reset FPGA via FPGA_DATA pin
- */
- SET_FPGA(FPGA_PRG | FPGA_CLK);
- udelay(1000); /* wait 1ms */
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
- udelay(1000); /* wait 1ms */
-
- /*
- * Check if magic for pci reconfig is written
- */
- magic = (unsigned int *)0x00000004;
- if (*magic == PCI_RECONFIG_MAGIC) {
- /*
- * Rewrite pci config regs (only after soft-reset with magic set)
- */
- ptr = (unsigned int *)PCI_REGS_ADDR;
- if (crc32(0, (uchar *)PCI_REGS_ADDR+4, PCI_REGS_LEN-4) == *ptr) {
- puts("Restoring PCI Configurations Regs!\n");
- ptr = (unsigned int *)PCI_REGS_ADDR + 1;
- for (i=0; i<0x40; i+=4) {
- pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
- }
- }
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- *magic = 0; /* clear pci reconfig magic again */
- }
-
- /*
- * Decrease PLB latency timeout and reduce priority of the PCI bridge master
- */
-#define PCI0_BRDGOPT1 0x4a
- pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
-
- /*
- * Enable fairness and high bus utilization
- */
- mtdcr(PLB0_ACR, 0x98000000);
-
- free(dst);
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming PCI405");
- } else {
- puts (str);
- }
-
- gd->board_type = board_revision();
- printf(" (Rev 1.%ld", gd->board_type);
-
- if (gd->board_type >= 2) {
- unsigned long CPC0_CR0Reg;
- unsigned long value;
-
- /*
- * Setup GPIO pins (Trace/GPIO1 to GPIO)
- */
- CPC0_CR0Reg = mfdcr(CPC0_CR0);
- mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
- out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
- out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
- udelay(1000); /* wait some time before reading input */
- value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */
- if (value) {
- puts(", 33 MHz PCI");
- } else {
- puts(", 66 MHz PCI");
- }
- }
-
- puts(")\n");
-
- return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-#define UART1_MCR 0xef600404
-int wpeeprom(int wp)
-{
- int wp_state = wp;
-
- if (wp == 1) {
- out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
- } else if (wp == 0) {
- out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
- } else {
- if (in_8((void *)UART1_MCR) & 0x02) {
- wp_state = 0;
- } else {
- wp_state = 1;
- }
- }
- return wp_state;
-}
-
-int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int wp = -1;
- if (argc >= 2) {
- if (argv[1][0] == '1') {
- wp = 1;
- } else if (argv[1][0] == '0') {
- wp = 0;
- }
- }
-
- wp = wpeeprom(wp);
- printf("EEPROM write protection %s\n", wp ? "ENABLED" : "DISABLED");
- return 0;
-}
-
-U_BOOT_CMD(
- wpeeprom, 2, 1, do_wpeeprom,
- "Check/Enable/Disable I2C EEPROM write protection",
- "wpeeprom\n"
- " - check I2C EEPROM write protection state\n"
- "wpeeprom 1\n"
- " - enable I2C EEPROM write protection\n"
- "wpeeprom 0\n"
- " - disable I2C EEPROM write protection"
-);
diff --git a/board/esd/pci405/pci405.h b/board/esd/pci405/pci405.h
deleted file mode 100644
index a62c9c2..0000000
--- a/board/esd/pci405/pci405.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PCI405_H_
-#define _PCI405_H_
-
-#define PCI_REGS_LEN 0x100
-#define PCI_REGS_ADDR ((unsigned long)0x01000000 - PCI_REGS_LEN)
-
-#define PCI_RECONFIG_MAGIC 0x07081967
-
-#endif /* _PCI405_H_ */
diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S
deleted file mode 100644
index 03eaf97..0000000
--- a/board/esd/pci405/writeibm.S
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0 IBM-pibs
- */
-/*----------------------------------------------------------------------------- */
-/* Function: ext_bus_cntlr_init */
-/* Description: Initializes the External Bus Controller for the external */
-/* peripherals. IMPORTANT: For pass1 this code must run from */
-/* cache since you can not reliably change a peripheral banks */
-/* timing register (pbxap) while running code from that bank. */
-/* For ex., since we are running from ROM on bank 0, we can NOT */
-/* execute the code that modifies bank 0 timings from ROM, so */
-/* we run it from cache. */
-/* Bank 0 - Flash and SRAM */
-/* Bank 1 - NVRAM/RTC */
-/* Bank 2 - Keyboard/Mouse controller */
-/* Bank 3 - IR controller */
-/* Bank 4 - not used */
-/* Bank 5 - not used */
-/* Bank 6 - not used */
-/* Bank 7 - FPGA registers */
-/*----------------------------------------------------------------------------- */
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl write_without_sync
-write_without_sync:
- /*
- * Write one values to host via pci busmastering
- * ptr = 0xc0000000 -> 0x01000000 (PCI)
- * *ptr = 0x01234567;
- */
- addi r31,0,0
- lis r31,0xc000
-
-start1:
- lis r0,0x0123
- ori r0,r0,0x4567
- stw r0,0(r31)
-
- /*
- * Read one value back
- * ptr = (volatile unsigned long *)addr;
- * val = *ptr;
- */
-
- lwz r0,0(r31)
-
- /*
- * One pci config write
- * ibmPciConfigWrite(0x2e, 2, 0x1234);
- */
- /* subsystem id */
-
- li r4,0x002C
- oris r4,r4,0x8000
- lis r3,0xEEC0
- stwbrx r4,0,r3
-
- li r5,0x1234
- ori r3,r3,0x4
- stwbrx r5,0,r3
-
- b start1
-
- blr /* never reached !!!! */
-
- .globl write_with_sync
-write_with_sync:
- /*
- * Write one values to host via pci busmastering
- * ptr = 0xc0000000 -> 0x01000000 (PCI)
- * *ptr = 0x01234567;
- */
- addi r31,0,0
- lis r31,0xc000
-
-start2:
- lis r0,0x0123
- ori r0,r0,0x4567
- stw r0,0(r31)
-
- /*
- * Read one value back
- * ptr = (volatile unsigned long *)addr;
- * val = *ptr;
- */
-
- lwz r0,0(r31)
-
- /*
- * One pci config write
- * ibmPciConfigWrite(0x2e, 2, 0x1234);
- */
- /* subsystem id */
-
- li r4,0x002C
- oris r4,r4,0x8000
- lis r3,0xEEC0
- stwbrx r4,0,r3
- sync
-
- li r5,0x1234
- ori r3,r3,0x4
- stwbrx r5,0,r3
- sync
-
- b start2
-
- blr /* never reached !!!! */
-
- .globl write_with_less_sync
-write_with_less_sync:
- /*
- * Write one values to host via pci busmastering
- * ptr = 0xc0000000 -> 0x01000000 (PCI)
- * *ptr = 0x01234567;
- */
- addi r31,0,0
- lis r31,0xc000
-
-start2b:
- lis r0,0x0123
- ori r0,r0,0x4567
- stw r0,0(r31)
-
- /*
- * Read one value back
- * ptr = (volatile unsigned long *)addr;
- * val = *ptr;
- */
-
- lwz r0,0(r31)
-
- /*
- * One pci config write
- * ibmPciConfigWrite(0x2e, 2, 0x1234);
- */
- /* subsystem id */
-
- li r4,0x002C
- oris r4,r4,0x8000
- lis r3,0xEEC0
- stwbrx r4,0,r3
- sync
-
- li r5,0x1234
- ori r3,r3,0x4
- stwbrx r5,0,r3
-/* sync */
-
- b start2b
-
- blr /* never reached !!!! */
-
- .globl write_with_more_sync
-write_with_more_sync:
- /*
- * Write one values to host via pci busmastering
- * ptr = 0xc0000000 -> 0x01000000 (PCI)
- * *ptr = 0x01234567;
- */
- addi r31,0,0
- lis r31,0xc000
-
-start3:
- lis r0,0x0123
- ori r0,r0,0x4567
- stw r0,0(r31)
- sync
-
- /*
- * Read one value back
- * ptr = (volatile unsigned long *)addr;
- * val = *ptr;
- */
-
- lwz r0,0(r31)
- sync
-
- /*
- * One pci config write
- * ibmPciConfigWrite(0x2e, 2, 0x1234);
- */
- /* subsystem id (PCIC0_SBSYSVID)*/
-
- li r4,0x002C
- oris r4,r4,0x8000
- lis r3,0xEEC0
- stwbrx r4,0,r3
- sync
-
- li r5,0x1234
- ori r3,r3,0x4
- stwbrx r5,0,r3
- sync
-
- b start3
-
- blr /* never reached !!!! */