diff options
Diffstat (limited to 'board/esd/hh405')
| -rw-r--r-- | board/esd/hh405/hh405.c | 166 | ||||
| -rw-r--r-- | board/esd/hh405/u-boot.lds | 19 |
2 files changed, 102 insertions, 83 deletions
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index ae3bc80..eab952c 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -29,6 +29,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> #include <malloc.h> #include <pci.h> @@ -36,6 +37,26 @@ DECLARE_GLOBAL_DATA_PTR; +/* FPGA internal regs */ +#define FPGA_CTRL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000)) +#define FPGA_STATUS ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002)) +#define FPGA_CTR ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004)) +#define FPGA_BL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006)) + +/* FPGA Control Reg */ +#define FPGA_CTRL_REV0 0x0001 +#define FPGA_CTRL_REV1 0x0002 +#define FPGA_CTRL_VGA0_BL 0x0004 +#define FPGA_CTRL_VGA0_BL_MODE 0x0008 +#define FPGA_CTRL_CF_RESET 0x0040 +#define FPGA_CTRL_PS2_PWR 0x0080 +#define FPGA_CTRL_CF_PWRN 0x0100 /* low active */ +#define FPGA_CTRL_CF_BUS_EN 0x0200 +#define FPGA_CTRL_LCD_CLK 0x7000 /* mask for lcd clock */ +#define FPGA_CTRL_OW_ENABLE 0x8000 + +#define FPGA_STATUS_CF_DETECT 0x8000 + #ifdef CONFIG_VIDEO_SM501 #define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ @@ -297,22 +318,22 @@ int board_revision(void) /* * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO) */ - osrh_reg = in32(GPIO0_OSRH); - isr1h_reg = in32(GPIO0_ISR1H); - tcr_reg = in32(GPIO0_TCR); - out32(GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */ - out32(GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */ - out32(GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */ + osrh_reg = in_be32((void *)GPIO0_OSRH); + isr1h_reg = in_be32((void *)GPIO0_ISR1H); + tcr_reg = in_be32((void *)GPIO0_TCR); + out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */ + out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */ + out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */ udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x80400000; /* get config bits */ + value = in_be32((void *)GPIO0_IR) & 0x80400000; /* get config bits */ /* * Restore GPIO settings */ - out32(GPIO0_OSRH, osrh_reg); /* output select */ - out32(GPIO0_ISR1H, isr1h_reg); /* input select */ - out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ + out_be32((void *)GPIO0_OSRH, osrh_reg); /* output select */ + out_be32((void *)GPIO0_ISR1H, isr1h_reg); /* input select */ + out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */ if (value & 0x80000000) { /* Revision 1.0 or 1.1 detected */ @@ -353,7 +374,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc(epcr, 0xa8400000); /* ebc always driven */ return 0; } @@ -362,27 +383,26 @@ int cf_enable(void) { int i; - volatile unsigned short *fpga_ctrl = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); - volatile unsigned short *fpga_status = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2); - if (gd->board_type >= 2) { - if (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT) { - if (!(*fpga_ctrl & CONFIG_SYS_FPGA_CTRL_CF_BUS_EN)) { - *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_PWRN; + if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) { + if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) { + out_be16(FPGA_CTRL, + in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN); for (i=0; i<300; i++) udelay(1000); - *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_BUS_EN; + out_be16(FPGA_CTRL, + in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN); for (i=0; i<20; i++) udelay(1000); } } else { - *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_BUS_EN; - *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_PWRN; + out_be16(FPGA_CTRL, + in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN); + out_be16(FPGA_CTRL, + in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN); } } @@ -391,12 +411,6 @@ int cf_enable(void) int misc_init_r (void) { - volatile unsigned short *fpga_ctrl = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); - volatile unsigned short *lcd_contrast = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4); - volatile unsigned short *lcd_backlight = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6); unsigned char *dst; ulong len = sizeof(fpgadata); int status; @@ -460,36 +474,43 @@ int misc_init_r (void) /* * Reset FPGA via FPGA_INIT pin */ - out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */ + /* setup FPGA_INIT as output */ + out_be32((void *)GPIO0_TCR, + in_be32((void *)GPIO0_TCR) | FPGA_INIT); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) & ~FPGA_INIT); /* reset low */ udelay(1000); /* wait 1ms */ - out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */ + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) | FPGA_INIT); /* reset high */ udelay(1000); /* wait 1ms */ /* * Write Board revision into FPGA */ - *fpga_ctrl |= gd->board_type & 0x0003; + out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003)); /* * Setup and enable EEPROM write protection */ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); /* * Reset touch-screen controller */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST); udelay(1000); - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_TOUCH_RST); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST); /* * Enable power on PS/2 interface (with reset) */ - *fpga_ctrl &= ~(CONFIG_SYS_FPGA_CTRL_PS2_PWR); + out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR); for (i=0;i<500;i++) udelay(1000); - *fpga_ctrl |= (CONFIG_SYS_FPGA_CTRL_PS2_PWR); + out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR); /* * Get contrast value from environment variable @@ -498,7 +519,8 @@ int misc_init_r (void) if (str) { contrast0 = simple_strtol(str, NULL, 16); if (contrast0 > 255) { - printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0); + printf("ERROR: contrast0 value too high (0x%lx)!\n", + contrast0); contrast0 = 0xffffffff; } } @@ -512,8 +534,9 @@ int misc_init_r (void) /* * Switch backlight on */ - *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL; - *lcd_backlight = 0x0000; + out_be16(FPGA_CTRL, + in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL); + out_be16(FPGA_BL, 0x0000); lcd_setup(1, 0); lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, @@ -524,8 +547,9 @@ int misc_init_r (void) /* * Switch backlight on */ - *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_VGA0_BL; - *lcd_backlight = 0x0000; + out_be16(FPGA_CTRL, + in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL); + out_be16(FPGA_BL, 0x0000); lcd_setup(1, 0); lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM, @@ -537,19 +561,22 @@ int misc_init_r (void) * Set default display contrast voltage */ if (contrast0 == 0xffffffff) { - *lcd_contrast = 0x0082; + out_be16(FPGA_CTR, 0x0082); } else { - *lcd_contrast = contrast0; + out_be16(FPGA_CTR, contrast0); } - *lcd_backlight = 0xffff; + out_be16(FPGA_BL, 0xffff); /* * Switch backlight on */ - *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE; + out_be16(FPGA_CTRL, + in_be16(FPGA_CTRL) | + FPGA_CTRL_VGA0_BL | + FPGA_CTRL_VGA0_BL_MODE); /* * Set lcd clock (small epson) */ - *fpga_ctrl |= LCD_CLK_06250; + out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250); udelay(100); /* wait for 100 us */ lcd_setup(0, 1); @@ -562,19 +589,25 @@ int misc_init_r (void) * Set default display contrast voltage */ if (contrast0 == 0xffffffff) { - *lcd_contrast = 0x0060; + out_be16(FPGA_CTR, 0x0060); } else { - *lcd_contrast = contrast0; + out_be16(FPGA_CTR, contrast0); } - *lcd_backlight = 0xffff; + out_be16(FPGA_BL, 0xffff); /* * Switch backlight on */ - *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE; + out_be16(FPGA_CTRL, + in_be16(FPGA_CTRL) | + FPGA_CTRL_VGA0_BL | + FPGA_CTRL_VGA0_BL_MODE); /* * Set lcd clock (small epson), enable 1-wire interface */ - *fpga_ctrl |= LCD_CLK_08330 | CONFIG_SYS_FPGA_CTRL_OW_ENABLE; + out_be16(FPGA_CTRL, + in_be16(FPGA_CTRL) | + LCD_CLK_08330 | + FPGA_CTRL_OW_ENABLE); lcd_setup(0, 1); lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM, @@ -593,10 +626,10 @@ int misc_init_r (void) puts("VGA: SM501 with 8 MB "); if (strcmp(str, "ppc221") == 0) { printf("(800*600, %dbpp)\n", BPP); - *lcd_backlight = 0x002d; /* max. allowed brightness */ + out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */ } else if (strcmp(str, "ppc231") == 0) { printf("(1024*768, %dbpp)\n", BPP); - *lcd_backlight = 0x0000; + out_be16(FPGA_BL, 0x0000); } else { printf("Unsupported bd_type defined (%s) -> No display configured!\n", str); return 0; @@ -646,21 +679,21 @@ int checkboard (void) #ifdef CONFIG_IDE_RESET void ide_set_reset(int on) { - volatile unsigned short *fpga_mode = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL); - volatile unsigned short *fpga_status = - (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2); - - if (((gd->board_type >= 2) && (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT)) || + if (((gd->board_type >= 2) && + (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) || (gd->board_type < 2)) { /* * Assert or deassert CompactFlash Reset Pin */ if (on) { /* assert RESET */ cf_enable(); - *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET); + out_be16(FPGA_CTRL, + in_be16(FPGA_CTRL) & + ~FPGA_CTRL_CF_RESET); } else { /* release RESET */ - *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET; + out_be16(FPGA_CTRL, + in_be16(FPGA_CTRL) | + FPGA_CTRL_CF_RESET); } } } @@ -684,17 +717,20 @@ int eeprom_write_enable (unsigned dev_addr, int state) switch (state) { case 1: /* Enable write access, clear bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO_SINT2. */ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP); state = 0; break; default: /* Read current status back. */ - state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP)); + state = (0 == (in_be32((void *)GPIO0_OR) & + CONFIG_SYS_EEPROM_WP)); break; } } diff --git a/board/esd/hh405/u-boot.lds b/board/esd/hh405/u-boot.lds index 9697cc6..8c01016 100644 --- a/board/esd/hh405/u-boot.lds +++ b/board/esd/hh405/u-boot.lds @@ -57,22 +57,7 @@ SECTIONS .plt : { *(.plt) } .text : { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/4xx_uart.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/env_embedded.o(.text)*/ *(.text) *(.fixup) @@ -82,10 +67,8 @@ SECTIONS PROVIDE (etext = .); .rodata : { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } |