diff options
Diffstat (limited to 'board/esd/cpci405')
| -rw-r--r-- | board/esd/cpci405/cpci405.c | 22 | ||||
| -rw-r--r-- | board/esd/cpci405/flash.c | 20 |
2 files changed, 21 insertions, 21 deletions
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index a677c62..4c9ed2f 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -214,7 +214,7 @@ int ctermm2(void) int cpci405_host(void) { - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) return -1; /* yes, board is cpci405 host */ else return 0; /* no, board is cpci405 adapter */ @@ -222,14 +222,14 @@ int cpci405_host(void) int cpci405_version(void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); udelay(1000); /* wait some time before reading input */ @@ -238,7 +238,7 @@ int cpci405_version(void) /* * Restore GPIO settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); switch (value) { case 0x00180000: @@ -261,7 +261,7 @@ int cpci405_version(void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -283,8 +283,8 @@ int misc_init_r (void) /* * Setup GPIO pins (CS6+CS7 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, @@ -330,7 +330,7 @@ int misc_init_r (void) } /* restore gpio/cs settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); puts("FPGA: "); @@ -400,8 +400,8 @@ int misc_init_r (void) /* * Select cts (and not dsr) on uart1 */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return 0; } diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c index d535924..4fcf174 100644 --- a/board/esd/cpci405/flash.c +++ b/board/esd/cpci405/flash.c @@ -91,13 +91,13 @@ unsigned long flash_init (void) size_b1 = 1 << 20; } base_b1 = -size_b1; - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17); - mtdcr (ebccfgd, pbcr); + mtdcr (EBC0_CFGDATA, pbcr); #if 0 /* test-only */ - printf("size_b1=%x base_b1=%x pb1cr = %x\n", + printf("size_b1=%x base_b1=%x PB1CR = %x\n", size_b1, base_b1, pbcr); /* test-only */ #endif } @@ -108,13 +108,13 @@ unsigned long flash_init (void) size_b0 = 1 << 20; } base_b0 = base_b1 - size_b0; - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17); - mtdcr (ebccfgd, pbcr); + mtdcr (EBC0_CFGDATA, pbcr); #if 0 /* test-only */ - printf("size_b0=%x base_b0=%x pb0cr = %x\n", + printf("size_b0=%x base_b0=%x PB0CR = %x\n", size_b0, base_b0, pbcr); /* test-only */ #endif } |