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Diffstat (limited to 'board/ep82xxm/ep82xxm.c')
-rw-r--r--board/ep82xxm/ep82xxm.c266
1 files changed, 133 insertions, 133 deletions
diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c
index fe3f78e..27443d3 100644
--- a/board/ep82xxm/ep82xxm.c
+++ b/board/ep82xxm/ep82xxm.c
@@ -46,146 +46,146 @@ const iop_conf_t iop_conf_tab[4][32] = {
/* Port A */
{ /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 0, 0, 0, 0, 1 }, /* PA31 */
- /* PA30 */ { 0, 0, 0, 0, 0, 1 }, /* PA30 */
- /* PA29 */ { 0, 0, 0, 0, 0, 1 }, /* PA29 */
- /* PA28 */ { 0, 0, 0, 0, 0, 1 }, /* PA28 */
- /* PA27 */ { 0, 0, 0, 0, 0, 1 }, /* PA27 */
- /* PA26 */ { 0, 0, 0, 0, 0, 1 }, /* PA26 */
- /* PA25 */ { 0, 0, 0, 0, 0, 1 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 1 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 1 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { 0, 0, 0, 0, 0, 1 }, /* PA21 */
- /* PA20 */ { 0, 0, 0, 0, 0, 1 }, /* PA20 */
- /* PA19 */ { 0, 0, 0, 0, 0, 1 }, /* PA19 */
- /* PA18 */ { 0, 0, 0, 0, 0, 1 }, /* PA18 */
- /* PA17 */ { 0, 0, 0, 0, 0, 1 }, /* PA17 */
- /* PA16 */ { 0, 0, 0, 0, 0, 1 }, /* PA16 */
- /* PA15 */ { 0, 0, 0, 0, 0, 1 }, /* PA15 */
- /* PA14 */ { 0, 0, 0, 0, 0, 1 }, /* PA14 */
- /* PA13 */ { 0, 0, 0, 0, 0, 1 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 1 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 1 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 1 }, /* PA10 */
- /* PA9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC2 TxD */
- /* PA8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC2 RxD */
- /* PA7 */ { 0, 0, 0, 0, 0, 1 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 1 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 1 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 1 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 1 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 1 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 1 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 1 } /* PA0 */
+ /* PA31 */ { 0, 0, 0, 0, 0, 1 }, /* PA31 */
+ /* PA30 */ { 0, 0, 0, 0, 0, 1 }, /* PA30 */
+ /* PA29 */ { 0, 0, 0, 0, 0, 1 }, /* PA29 */
+ /* PA28 */ { 0, 0, 0, 0, 0, 1 }, /* PA28 */
+ /* PA27 */ { 0, 0, 0, 0, 0, 1 }, /* PA27 */
+ /* PA26 */ { 0, 0, 0, 0, 0, 1 }, /* PA26 */
+ /* PA25 */ { 0, 0, 0, 0, 0, 1 }, /* PA25 */
+ /* PA24 */ { 0, 0, 0, 0, 0, 1 }, /* PA24 */
+ /* PA23 */ { 0, 0, 0, 0, 0, 1 }, /* PA23 */
+ /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
+ /* PA21 */ { 0, 0, 0, 0, 0, 1 }, /* PA21 */
+ /* PA20 */ { 0, 0, 0, 0, 0, 1 }, /* PA20 */
+ /* PA19 */ { 0, 0, 0, 0, 0, 1 }, /* PA19 */
+ /* PA18 */ { 0, 0, 0, 0, 0, 1 }, /* PA18 */
+ /* PA17 */ { 0, 0, 0, 0, 0, 1 }, /* PA17 */
+ /* PA16 */ { 0, 0, 0, 0, 0, 1 }, /* PA16 */
+ /* PA15 */ { 0, 0, 0, 0, 0, 1 }, /* PA15 */
+ /* PA14 */ { 0, 0, 0, 0, 0, 1 }, /* PA14 */
+ /* PA13 */ { 0, 0, 0, 0, 0, 1 }, /* PA13 */
+ /* PA12 */ { 0, 0, 0, 0, 0, 1 }, /* PA12 */
+ /* PA11 */ { 0, 0, 0, 0, 0, 1 }, /* PA11 */
+ /* PA10 */ { 0, 0, 0, 0, 0, 1 }, /* PA10 */
+ /* PA9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC2 TxD */
+ /* PA8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC2 RxD */
+ /* PA7 */ { 0, 0, 0, 0, 0, 1 }, /* PA7 */
+ /* PA6 */ { 0, 0, 0, 0, 0, 1 }, /* PA6 */
+ /* PA5 */ { 0, 0, 0, 0, 0, 1 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 0, 0, 1 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 0, 0, 1 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 0, 0, 1 }, /* PA2 */
+ /* PA1 */ { 0, 0, 0, 0, 0, 1 }, /* PA1 */
+ /* PA0 */ { 0, 0, 0, 0, 0, 1 } /* PA0 */
},
/* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
- /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
+ /* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
},
/* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 CTS# */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3: TXD[0] */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
- /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* RxClk (CLK13) */
- /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* TxClk (CLK14) */
- /* PC17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* RxClk (CLK15) */
- /* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* TxClk (CLK16) */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 CD# */
- /* PC13 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CTS# */
- /* PC12 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CD# */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 CD# */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
- /* PC8 */ { 1, 1, 1, 0, 0, 0 }, /* SCC3 CTS# */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
+ /* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 CTS# */
+ /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
+ /* PC27 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3: TXD[0] */
+ /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
+ /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
+ /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
+ /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
+ /* PC19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* RxClk (CLK13) */
+ /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* TxClk (CLK14) */
+ /* PC17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* RxClk (CLK15) */
+ /* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* TxClk (CLK16) */
+ /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 CD# */
+ /* PC13 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CTS# */
+ /* PC12 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 CD# */
+ /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
+ /* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 CD# */
+ /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
+ /* PC8 */ { 1, 1, 1, 0, 0, 0 }, /* SCC3 CTS# */
+ /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
+ /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
+ /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
},
/* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
- /* PD30 */ { 1, 1, 1, 1, 0, 1 }, /* SCC1 TXD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS# */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
- /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
- /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS# */
- /* PD25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
- /* PD24 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 TXD */
- /* PD23 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 RTS# */
- /* PD22 */ { 0, 0, 0, 0, 0, 1 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 1 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 1 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 1 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 1 }, /* PD18 */
- /* PD17 */ { 0, 0, 0, 0, 0, 1 }, /* PD17 */
- /* PD16 */ { 0, 0, 0, 0, 0, 1 }, /* PD16 */
- /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 1 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 1 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 1 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 1 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC1 TxD */
- /* PD8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 RxD */
- /* PD7 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 SMSYN */
- /* PD6 */ { 0, 0, 0, 0, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 1 }, /* SCC1 TXD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS# */
+ /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
+ /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
+ /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS# */
+ /* PD25 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
+ /* PD24 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 TXD */
+ /* PD23 */ { 1, 1, 0, 1, 0, 0 }, /* SCC3 RTS# */
+ /* PD22 */ { 0, 0, 0, 0, 0, 1 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 0, 0, 1 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 0, 0, 1 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 0, 0, 1 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 0, 0, 1 }, /* PD18 */
+ /* PD17 */ { 0, 0, 0, 0, 0, 1 }, /* PD17 */
+ /* PD16 */ { 0, 0, 0, 0, 0, 1 }, /* PD16 */
+ /* PD15 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 1 }, /* I2C SCL */
+ /* PD13 */ { 0, 0, 0, 0, 0, 1 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 1 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 1 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 1 }, /* PD10 */
+ /* PD9 */ { 1, 1, 0, 1, 0, 1 }, /* SMC1 TxD */
+ /* PD8 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 RxD */
+ /* PD7 */ { 1, 1, 0, 0, 0, 1 }, /* SMC1 SMSYN */
+ /* PD6 */ { 0, 0, 0, 0, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 0, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 0, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
}
};
@@ -230,8 +230,8 @@ long int initdram(int board_type)
uint psdmr = CFG_PSDMR;
int i;
- unsigned char ramtmp;
- unsigned char *ramptr1 = (unsigned char *)0x00000110;
+ unsigned char ramtmp;
+ unsigned char *ramptr1 = (unsigned char *)0x00000110;
memctl->memc_mptpr = CFG_MPTPR;
generated by cgit v1.1 at 2024-11-07 16:03:59 +0000