diff options
Diffstat (limited to 'board/davinci/da8xxevm')
| -rw-r--r-- | board/davinci/da8xxevm/da850evm.c | 54 | ||||
| -rw-r--r-- | board/davinci/da8xxevm/hawkboard-ais-nand.cfg | 4 | ||||
| -rw-r--r-- | board/davinci/da8xxevm/hawkboard.c | 41 |
3 files changed, 93 insertions, 6 deletions
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 004d5ad..0c7aabb 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -36,6 +36,11 @@ #include <asm/errno.h> #include <hwconfig.h> +#ifdef CONFIG_DAVINCI_MMC +#include <mmc.h> +#include <asm/arch/sdmmc_defs.h> +#endif + DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_DRIVER_TI_EMAC @@ -204,11 +209,32 @@ int misc_init_r(void) return 0; } +#ifdef CONFIG_DAVINCI_MMC +static struct davinci_mmc mmc_sd0 = { + .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE, + .host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */ + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, + .version = MMC_CTLR_VERSION_2, +}; + +int board_mmc_init(bd_t *bis) +{ + mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID); + + /* Add slot-0 to mmc subsystem */ + return davinci_mmc_init(bis, &mmc_sd0); +} +#endif + static const struct pinmux_config gpio_pins[] = { #ifdef CONFIG_USE_NOR /* GP0[11] is required for NOR to work on Rev 3 EVMs */ { pinmux(0), 8, 4 }, /* GP0[11] */ #endif +#ifdef CONFIG_DAVINCI_MMC + /* GP0[11] is required for SD to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ +#endif }; const struct pinmux_resource pinmuxes[] = { @@ -236,6 +262,9 @@ const struct pinmux_resource pinmuxes[] = { PINMUX_ITEM(emifa_pins_nor), #endif PINMUX_ITEM(gpio_pins), +#ifdef CONFIG_DAVINCI_MMC + PINMUX_ITEM(mmc0_pins), +#endif }; const int pinmuxes_size = ARRAY_SIZE(pinmuxes); @@ -246,6 +275,9 @@ const struct lpsc_resource lpsc[] = { { DAVINCI_LPSC_EMAC }, /* image download */ { DAVINCI_LPSC_UART2 }, /* console */ { DAVINCI_LPSC_GPIO }, +#ifdef CONFIG_DAVINCI_MMC + { DAVINCI_LPSC_MMC_SD }, +#endif }; const int lpsc_size = ARRAY_SIZE(lpsc); @@ -303,7 +335,7 @@ int board_early_init_f(void) int board_init(void) { -#ifdef CONFIG_USE_NOR +#if defined(CONFIG_USE_NOR) || defined(CONFIG_DAVINCI_MMC) u32 val; #endif @@ -316,11 +348,11 @@ int board_init(void) * NAND CS setup - cycle counts based on da850evm NAND timings in the * Linux kernel @ 25MHz EMIFA */ - writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(1) | - DAVINCI_ABCR_WHOLD(0) | - DAVINCI_ABCR_RSETUP(0) | - DAVINCI_ABCR_RSTROBE(1) | + writel((DAVINCI_ABCR_WSETUP(2) | + DAVINCI_ABCR_WSTROBE(2) | + DAVINCI_ABCR_WHOLD(1) | + DAVINCI_ABCR_RSETUP(1) | + DAVINCI_ABCR_RSTROBE(4) | DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(1) | DAVINCI_ABCR_ASIZE_8BIT), @@ -354,6 +386,16 @@ int board_init(void) writel(val, GPIO_BANK0_REG_CLR_ADDR); #endif +#ifdef CONFIG_DAVINCI_MMC + /* Set the GPIO direction as output */ + clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); + + /* Set the output as high */ + val = readl(GPIO_BANK0_REG_SET_ADDR); + val |= (0x01 << 11); + writel(val, GPIO_BANK0_REG_SET_ADDR); +#endif + #ifdef CONFIG_DRIVER_TI_EMAC davinci_emac_mii_mode_sel(HAS_RMII); #endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/board/davinci/da8xxevm/hawkboard-ais-nand.cfg b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg new file mode 100644 index 0000000..2b12b6c --- /dev/null +++ b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg @@ -0,0 +1,4 @@ +# PLL0CFG0 PLL0CFG1 +PLL0 0x00180001 0x00000205 +# PLL1CFG0 PLL1CFG1 DRPYC1R SDCR SDTIMR1 SDTIMR2 SDRCR CLK2XSRC +DDR2 0x15010001 0x00000002 0x00000043 0x00134632 0x26492a09 0x7d13c722 0x00000249 0x00000000 diff --git a/board/davinci/da8xxevm/hawkboard.c b/board/davinci/da8xxevm/hawkboard.c index b694258..156cb7f 100644 --- a/board/davinci/da8xxevm/hawkboard.c +++ b/board/davinci/da8xxevm/hawkboard.c @@ -4,6 +4,7 @@ * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. <nsekhar@ti.com> * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> * Copyright (C) 2004 Texas Instruments. + * Copyright (C) 2012 Sughosh Ganu <urwithsughosh@gmail.com>. * * ---------------------------------------------------------------------------- * This program is free software; you can redistribute it and/or modify @@ -28,6 +29,7 @@ #include <asm/io.h> #include <asm/arch/davinci_misc.h> #include <asm/arch/pinmux_defs.h> +#include <asm/arch/da8xx-usb.h> #include <ns16550.h> DECLARE_GLOBAL_DATA_PTR; @@ -89,3 +91,42 @@ int misc_init_r(void) return 0; } + +int usb_phy_on(void) +{ + u32 timeout; + u32 cfgchip2; + + cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); + + cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | + CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ | + CFGCHIP2_USB1PHYCLKMUX); + cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON | + CFGCHIP2_REFFREQ_24MHZ | CFGCHIP2_USB2PHYCLKMUX | + CFGCHIP2_USB1SUSPENDM; + + writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); + + /* wait until the usb phy pll locks */ + timeout = DA8XX_USB_OTG_TIMEOUT; + while (timeout--) + if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD) + return 1; + + /* USB phy was not turned on */ + return 0; +} + +void usb_phy_off(void) +{ + u32 cfgchip2; + + /* + * Power down the on-chip PHY. + */ + cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); + cfgchip2 &= ~(CFGCHIP2_PHY_PLLON | CFGCHIP2_USB1SUSPENDM); + cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | CFGCHIP2_RESET; + writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); +} |