diff options
Diffstat (limited to 'board/davinci/common')
| -rw-r--r-- | board/davinci/common/psc.c | 65 | ||||
| -rw-r--r-- | board/davinci/common/psc.h | 4 |
2 files changed, 69 insertions, 0 deletions
diff --git a/board/davinci/common/psc.c b/board/davinci/common/psc.c index d538d51..28e2a4b 100644 --- a/board/davinci/common/psc.c +++ b/board/davinci/common/psc.c @@ -26,6 +26,14 @@ #include <common.h> #include <asm/arch/hardware.h> +#define PINMUX0_EMACEN (1 << 31) +#define PINMUX0_AECS5 (1 << 11) +#define PINMUX0_AECS4 (1 << 10) + +#define PINMUX1_I2C (1 << 7) +#define PINMUX1_UART1 (1 << 1) +#define PINMUX1_UART0 (1 << 0) + /* * The DM6446 includes two separate power domains: "Always On" and "DSP". The * "Always On" power domain is always on when the chip is on. The "Always On" @@ -115,3 +123,60 @@ void dsp_on(void) REG(PSC_GBLCTL) &= ~0x1f; } #endif /* CONFIG_SYS_USE_DSPLINK */ + +void davinci_enable_uart0(void) +{ + lpsc_on(DAVINCI_LPSC_UART0); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= PINMUX1_UART0; +} + +#ifdef CONFIG_DRIVER_TI_EMAC +void davinci_enable_emac(void) +{ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable EMAC. */ + REG(PINMUX0) |= PINMUX0_EMACEN; +} +#endif + +void davinci_enable_i2c(void) +{ + lpsc_on(DAVINCI_LPSC_I2C); + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= PINMUX1_I2C; +} + +void davinci_errata_workarounds(void) +{ + /* + * Workaround for TMS320DM6446 errata 1.3.22: + * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset + * Revision(s) Affected: 1.3 and earlier + */ + REG(PSC_SILVER_BULLET) = 0; + + /* + * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) + * as suggested in TMS320DM6446 errata 2.1.2: + * + * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions + * low priority modules can occupy the bus and prevent high priority + * modules like the VPSS from getting the required DDR2 throughput. + * A hex value of 0x20 should provide a good ARM (cache enabled) + * performance and still allow good utilization by the VPSS or other + * modules. + */ + REG(VBPR) = 0x20; +} diff --git a/board/davinci/common/psc.h b/board/davinci/common/psc.h index 6ab2575..b2dd7b5 100644 --- a/board/davinci/common/psc.h +++ b/board/davinci/common/psc.h @@ -24,5 +24,9 @@ void lpsc_on(unsigned int id); void dsp_on(void); +void davinci_enable_uart0(void); +void davinci_enable_emac(void); +void davinci_enable_i2c(void); +void davinci_errata_workarounds(void); #endif /* __PSC_H */ |