diff options
Diffstat (limited to 'board/cray')
| -rw-r--r-- | board/cray/L1/flash.c | 471 | ||||
| -rw-r--r-- | board/cray/L1/init.S | 147 |
2 files changed, 618 insertions, 0 deletions
diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c new file mode 100644 index 0000000..6d66905 --- /dev/null +++ b/board/cray/L1/flash.c @@ -0,0 +1,471 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +/* + * Modified July 20, 2001 + * Strip down to support ONLY the AMD29F032B. + * Dave Updegraff - Cray, Inc. dave@cray.com + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + +/* The flash chip we use... */ +#define AMD_ID_F032B 0x41 /* 29F032B ID 32 Mbit,64 64Kx8 sectors */ +#define FLASH_AM320B 0x0009 + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info); +static int write_word (flash_info_t *info, ulong dest, ulong data); +static void flash_get_offsets (ulong base, flash_info_t *info); + +#define ADDR0 0x5555 +#define ADDR1 0x2aaa +#define FLASH_WORD_SIZE unsigned char + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + unsigned long size_b0, size_b1; + int i; + + /* Init: no FLASHes known */ + for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + } + + /* Static FLASH Bank configuration here - FIXME XXX */ + + size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); + + if (flash_info[0].flash_id == FLASH_UNKNOWN) { + printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", + size_b0, size_b0<<20); + } + + /* Only one bank */ + if (CFG_MAX_FLASH_BANKS == 1) + { + /* Setup offsets */ + flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]); + +#if 0 + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + FLASH_BASE0_PRELIM, + FLASH_BASE0_PRELIM+CFG_MONITOR_LEN-1, + &flash_info[0]); +#endif + size_b1 = 0 ; + flash_info[0].size = size_b0; + } + + return (size_b0 + size_b1); +} + + + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t *info) +{ + int i; + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t *info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: printf ("AMD "); break; + default: printf ("Unknown Vendor "); break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM320B:printf ("AM29F032B (32 Mbit 64x64KB uniform sectors)\n"); + break; + default: printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count-1)) + size = info->start[i+1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k=0; k<size; k++) + { + if (*flash++ != 0xffffffff) + { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf ("\n "); + + printf (" %08lX%s%s", + info->start[i], + erased ? " E" : " ", + info->protect[i] ? "RO " : " " + ); + } + printf ("\n"); +} + +/*----------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------- + */ + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (vu_long *addr, flash_info_t *info) +{ + short i; + FLASH_WORD_SIZE value; + ulong base = (ulong)addr; + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr; + + /* Write auto select command: read Manufacturer ID */ + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090; + + value = addr2[0]; + + switch (value) { + case (FLASH_WORD_SIZE)AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + + switch (value) { + case (FLASH_WORD_SIZE)AMD_ID_F032B: + info->flash_id += FLASH_AM320B; + info->sector_count = 64; + info->size = 0x0400000; /* => 4 MB */ + break; + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + + } + + /* set up sector start address table */ + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]); + info->protect[i] = addr2[2] & 1; + } + + /* + * Prevent writes to uninitialized FLASH. + */ + if (info->flash_id != FLASH_UNKNOWN) { + addr2 = (FLASH_WORD_SIZE *)info->start[0]; + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + } + + return (info->size); +} + +int wait_for_DQ7(flash_info_t *info, int sect) +{ + ulong start, now, last; + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); + + start = get_timer (0); + last = start; + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } + } + return 0; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf ("- missing\n"); + } else { + printf ("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect=s_first; sect<=s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf ("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect<=s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]); + printf("Erasing sector %p\n", addr2); + + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080; + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */ + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay (1000); + + /* reset to read mode */ + addr = (FLASH_WORD_SIZE *)info->start[0]; + addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */ + + printf (" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i=0, cp=wp; i<l; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + for (; i<4 && cnt>0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt==0 && i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i=0; i<4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i<4; ++i, ++cp) { + data = (data << 8) | (*(uchar *)cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word (flash_info_t *info, ulong dest, ulong data) +{ + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]); + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest; + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data; + ulong start; + int flag; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((volatile FLASH_WORD_SIZE *)dest) & + (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) { + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++) + { + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA; + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055; + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer (0); + while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != + (data2[i] & (FLASH_WORD_SIZE)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +/*----------------------------------------------------------------------- + */ diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S new file mode 100644 index 0000000..acc5205 --- /dev/null +++ b/board/cray/L1/init.S @@ -0,0 +1,147 @@ +/*------------------------------------------------------------------------------+ */ +/* */ +/* This source code has been made available to you by IBM on an AS-IS */ +/* basis. Anyone receiving this source is licensed under IBM */ +/* copyrights to use it in any way he or she deems fit, including */ +/* copying it, modifying it, compiling it, and redistributing it either */ +/* with or without modifications. No license under IBM patents or */ +/* patent applications is to be implied by the copyright license. */ +/* */ +/* Any user of this software should understand that IBM cannot provide */ +/* technical support for this software and will not be responsible for */ +/* any consequences resulting from the use of this software. */ +/* */ +/* Any person who transfers this source code or any derivative work */ +/* must include the IBM copyright notice, this paragraph, and the */ +/* preceding two paragraphs in the transferred software. */ +/* */ +/* COPYRIGHT I B M CORPORATION 1995 */ +/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ +/*------------------------------------------------------------------------------- */ + +/*----------------------------------------------------------------------------- */ +/* Function: ext_bus_cntlr_init */ +/* Description: Initializes the External Bus Controller for the external */ +/* peripherals. IMPORTANT: For pass1 this code must run from */ +/* cache since you can not reliably change a peripheral banks */ +/* timing register (pbxap) while running code from that bank. */ +/* For ex., since we are running from ROM on bank 0, we can NOT */ +/* execute the code that modifies bank 0 timings from ROM, so */ +/* we run it from cache. */ +/* Bank 0 - Flash and SRAM */ +/* Bank 1 - NVRAM/RTC */ +/* Bank 2 - Keyboard/Mouse controller */ +/* Bank 3 - IR controller */ +/* Bank 4 - not used */ +/* Bank 5 - not used */ +/* Bank 6 - not used */ +/* Bank 7 - FPGA registers */ +/*-----------------------------------------------------------------------------#include <config.h> */ +#include <ppc4xx.h> + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + +/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */ +/* except for #1 which we use for DMA'ing to IOCA-like things, so the */ +/* control registers to set that up are determined by what we've */ +/* empirically discovered work there. */ + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + mflr r4 /* save link register */ + bl ..getAddr +..getAddr: + mflr r3 /* get address of ..getAddr */ + mtlr r4 /* restore link register */ + addi r4,0,14 /* set ctr to 10; used to prefetch */ + mtctr r4 /* 10 cache lines to fit this function */ + /* in cache (gives us 8x10=80 instrctns) */ +..ebcloop: + icbt r0,r3 /* prefetch cache line for addr in r3 */ + addi r3,r3,32 /* move to next cache line */ + bdnz ..ebcloop /* continue for 10 cache lines */ + + /*------------------------------------------------------------------- */ + /* Delay to ensure all accesses to ROM are complete before changing */ + /* bank 0 timings. 200usec should be enough. */ + /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ + /*------------------------------------------------------------------- */ + addis r3,0,0x0 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 +..spinlp: + bdnz ..spinlp /* spin loop */ + + + /*---------------------------------------------------------------------- */ + /* Peripheral Bank 0 (Flash) initialization */ + /*---------------------------------------------------------------------- */ + /* 0x7F8FFE80 slowest boot */ + addi r4,0,pb0ap + mtdcr ebccfga,r4 + addis r4,0,0x9B01 + ori r4,r4,0x5480 + mtdcr ebccfgd,r4 + + addi r4,0,pb0cr + mtdcr ebccfga,r4 + addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ + ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ + mtdcr ebccfgd,r4 + + blr + + /*---------------------------------------------------------------------- */ + /* Peripheral Bank 1 (NVRAM/RTC) initialization */ + /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */ + /* and we do DMA on it. The ConfigurationRegister part is threfore */ + /* almost arbitrary, except that our linux driver needs to know the */ + /* address, but it can query, it.. */ + /* */ + /* The AccessParameter is CRITICAL, */ + /* thouch, since it needs to agree with the electrical timings on the */ + /* IOCA parallel interface. That value is: 0x0185,4380 */ + /* BurstModeEnable BME=0 */ + /* TransferWait TWT=3 */ + /* ChipSelectOnTiming CSN=1 */ + /* OutputEnableOnTimimg OEN=1 */ + /* WriteByteEnableOnTiming WBN=1 */ + /* WriteByteEnableOffTiming WBF=0 */ + /* TransferHold TH=1 */ + /* ReadyEnable RE=1 */ + /* SampleOnReady SOR=1 */ + /* ByteEnableMode BEM=0 */ + /* ParityEnable PEN=0 */ + /* all reserved bits=0 */ + /*---------------------------------------------------------------------- */ + /*---------------------------------------------------------------------- */ + addi r4,0,pb1ap + mtdcr ebccfga,r4 + addis r4,0,0x0185 /* hiword */ + ori r4,r4,0x4380 /* loword */ + mtdcr ebccfgd,r4 + + addi r4,0,pb1cr + mtdcr ebccfga,r4 + addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ + ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ + mtdcr ebccfgd,r4 + + blr + +/*----------------------------------------------------------------------------- */ +/* Function: sdram_init */ +/* Description: Configures SDRAM memory banks. */ +/* NOTE: for CrayL1 we have ECC memory, so enable it. */ +/*....now done in C in L1.c:init_sdram for readability. */ +/*----------------------------------------------------------------------------- */ + .globl sdram_init + +sdram_init: + blr |