diff options
Diffstat (limited to 'board/cds')
| -rw-r--r-- | board/cds/common/ft_board.c | 30 | ||||
| -rw-r--r-- | board/cds/mpc8548cds/mpc8548cds.c | 32 |
2 files changed, 61 insertions, 1 deletions
diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c index 77d1d85..a897d04 100644 --- a/board/cds/common/ft_board.c +++ b/board/cds/common/ft_board.c @@ -24,9 +24,35 @@ #if defined(CONFIG_OF_FLAT_TREE) #include <ft_build.h> +#include "cadmus.h" + extern void ft_cpu_setup(void *blob, bd_t *bd); -#endif +static void cds_pci_fixup(void *blob) +{ + int len; + u32 *map; + int slot; + int i; + + map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len); + + len /= sizeof(u32); + + slot = get_pci_slot(); + + for (i=0;i<len;i+=7) { + /* We rotate the interrupt pins so that the mapping + * changes depending on the slot the carrier card is in. + */ + int j; + + map[3] = ((map[3] + slot - 2) % 4) + 1; + + map+=7; + } +} +#endif #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) void @@ -45,5 +71,7 @@ ft_board_setup(void *blob, bd_t *bd) *p++ = cpu_to_be32(bd->bi_memstart); *p = cpu_to_be32(bd->bi_memsize); } + + cds_pci_fixup(blob); } #endif diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 6eedb4a..66219e3 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -27,6 +27,7 @@ #include <asm/processor.h> #include <asm/immap_85xx.h> #include <spd.h> +#include <miiphy.h> #include "../common/cadmus.h" #include "../common/eeprom.h" @@ -327,3 +328,34 @@ pci_init_board(void) pci_mpc85xx_init(&hose); #endif } + +int last_stage_init(void) +{ + unsigned int temp; + + /* Change the resistors for the PHY */ + /* This is needed to get the RGMII working for the 1.3+ + * CDS cards */ + if (get_board_version() == 0x13) { + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 29, 18); + + miiphy_read(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, &temp); + + temp = (temp & 0xf03f); + temp |= 2 << 9; /* 36 ohm */ + temp |= 2 << 6; /* 39 ohm */ + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, temp); + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 29, 3); + + miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + TSEC1_PHY_ADDR, 30, 0x8000); + } + + return 0; +} |