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-rw-r--r--board/atmel/at91cap9adk/nand.c37
-rw-r--r--board/atmel/at91sam9260ek/nand.c37
-rw-r--r--board/atmel/at91sam9261ek/nand.c37
-rw-r--r--board/atmel/at91sam9263ek/nand.c37
-rw-r--r--board/atmel/at91sam9rlek/nand.c37
5 files changed, 90 insertions, 95 deletions
diff --git a/board/atmel/at91cap9adk/nand.c b/board/atmel/at91cap9adk/nand.c
index 0432ef1..1dec558 100644
--- a/board/atmel/at91cap9adk/nand.c
+++ b/board/atmel/at91cap9adk/nand.c
@@ -37,36 +37,35 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- switch (cmd) {
- case NAND_CTL_SETCLE:
- IO_ADDR_W |= MASK_CLE;
- break;
- case NAND_CTL_SETALE:
- IO_ADDR_W |= MASK_ALE;
- break;
- case NAND_CTL_CLRNCE:
- at91_set_gpio_value(AT91_PIN_PD15, 1);
- break;
- case NAND_CTL_SETNCE:
- at91_set_gpio_value(AT91_PIN_PD15, 0);
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
}
- this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
int board_nand_init(struct nand_chip *nand)
{
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
- nand->hwcontrol = at91cap9adk_nand_hwcontrol;
+ nand->cmd_ctrl = at91cap9adk_nand_hwcontrol;
nand->chip_delay = 20;
return 0;
diff --git a/board/atmel/at91sam9260ek/nand.c b/board/atmel/at91sam9260ek/nand.c
index 9738f0f..665e35c 100644
--- a/board/atmel/at91sam9260ek/nand.c
+++ b/board/atmel/at91sam9260ek/nand.c
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- switch (cmd) {
- case NAND_CTL_SETCLE:
- IO_ADDR_W |= MASK_CLE;
- break;
- case NAND_CTL_SETALE:
- IO_ADDR_W |= MASK_ALE;
- break;
- case NAND_CTL_CLRNCE:
- at91_set_gpio_value(AT91_PIN_PC14, 1);
- break;
- case NAND_CTL_SETNCE:
- at91_set_gpio_value(AT91_PIN_PC14, 0);
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
}
- this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
- nand->hwcontrol = at91sam9260ek_nand_hwcontrol;
+ nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
nand->dev_ready = at91sam9260ek_nand_ready;
nand->chip_delay = 20;
diff --git a/board/atmel/at91sam9261ek/nand.c b/board/atmel/at91sam9261ek/nand.c
index 35b26db..fccb9d7 100644
--- a/board/atmel/at91sam9261ek/nand.c
+++ b/board/atmel/at91sam9261ek/nand.c
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 22) /* our ALE is AD22 */
#define MASK_CLE (1 << 21) /* our CLE is AD21 */
-static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- switch (cmd) {
- case NAND_CTL_SETCLE:
- IO_ADDR_W |= MASK_CLE;
- break;
- case NAND_CTL_SETALE:
- IO_ADDR_W |= MASK_ALE;
- break;
- case NAND_CTL_CLRNCE:
- at91_set_gpio_value(AT91_PIN_PC14, 1);
- break;
- case NAND_CTL_SETNCE:
- at91_set_gpio_value(AT91_PIN_PC14, 0);
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
}
- this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9261ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
- nand->hwcontrol = at91sam9261ek_nand_hwcontrol;
+ nand->cmd_ctrl = at91sam9261ek_nand_hwcontrol;
nand->dev_ready = at91sam9261ek_nand_ready;
nand->chip_delay = 20;
diff --git a/board/atmel/at91sam9263ek/nand.c b/board/atmel/at91sam9263ek/nand.c
index 5079972..250ec7f 100644
--- a/board/atmel/at91sam9263ek/nand.c
+++ b/board/atmel/at91sam9263ek/nand.c
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- switch (cmd) {
- case NAND_CTL_SETCLE:
- IO_ADDR_W |= MASK_CLE;
- break;
- case NAND_CTL_SETALE:
- IO_ADDR_W |= MASK_ALE;
- break;
- case NAND_CTL_CLRNCE:
- at91_set_gpio_value(AT91_PIN_PD15, 1);
- break;
- case NAND_CTL_SETNCE:
- at91_set_gpio_value(AT91_PIN_PD15, 0);
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
}
- this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
- nand->hwcontrol = at91sam9263ek_nand_hwcontrol;
+ nand->cmd_ctrl = at91sam9263ek_nand_hwcontrol;
nand->dev_ready = at91sam9263ek_nand_ready;
nand->chip_delay = 20;
diff --git a/board/atmel/at91sam9rlek/nand.c b/board/atmel/at91sam9rlek/nand.c
index 5af1a31..eb342b8 100644
--- a/board/atmel/at91sam9rlek/nand.c
+++ b/board/atmel/at91sam9rlek/nand.c
@@ -37,27 +37,26 @@
#define MASK_ALE (1 << 21) /* our ALE is AD21 */
#define MASK_CLE (1 << 22) /* our CLE is AD22 */
-static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd,
+ int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
- ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
- IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
- switch (cmd) {
- case NAND_CTL_SETCLE:
- IO_ADDR_W |= MASK_CLE;
- break;
- case NAND_CTL_SETALE:
- IO_ADDR_W |= MASK_ALE;
- break;
- case NAND_CTL_CLRNCE:
- at91_set_gpio_value(AT91_PIN_PB6, 1);
- break;
- case NAND_CTL_SETNCE:
- at91_set_gpio_value(AT91_PIN_PB6, 0);
- break;
+ if (ctrl & NAND_CTRL_CHANGE) {
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+
+ at91_set_gpio_value(AT91_PIN_PB6, !(ctrl & NAND_NCE));
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
}
- this->IO_ADDR_W = (void *) IO_ADDR_W;
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
}
static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
@@ -67,11 +66,11 @@ static int at91sam9rlek_nand_ready(struct mtd_info *mtd)
int board_nand_init(struct nand_chip *nand)
{
- nand->eccmode = NAND_ECC_SOFT;
+ nand->ecc.mode = NAND_ECC_SOFT;
#ifdef CFG_NAND_DBW_16
nand->options = NAND_BUSWIDTH_16;
#endif
- nand->hwcontrol = at91sam9rlek_nand_hwcontrol;
+ nand->cmd_ctrl = at91sam9rlek_nand_hwcontrol;
nand->dev_ready = at91sam9rlek_nand_ready;
nand->chip_delay = 20;
generated by cgit v1.1 at 2024-11-17 13:23:11 +0000