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-rw-r--r--board/atc/atc.c35
-rw-r--r--board/atc/config.mk2
-rw-r--r--board/atc/flash.c36
-rw-r--r--board/atc/ti113x.c8
4 files changed, 40 insertions, 41 deletions
diff --git a/board/atc/atc.c b/board/atc/atc.c
index 79527f4..936c031 100644
--- a/board/atc/atc.c
+++ b/board/atc/atc.c
@@ -281,7 +281,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
*/
maxsize = (1 + (~orx | 0x7fff)) / 2;
- /* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+ /* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
* we are configuring CS1 if base != 0
*/
sdmr_ptr = &memctl->memc_psdmr;
@@ -306,7 +306,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
*/
*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -317,7 +317,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
+ *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
@@ -331,7 +331,7 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
int misc_init_r(void)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint));
@@ -342,37 +342,37 @@ int misc_init_r(void)
phys_size_t initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
ulong size8, size9;
#endif
long psize;
psize = 8 * 1024 * 1024;
- memctl->memc_mptpr = CFG_MPTPR;
- memctl->memc_psrt = CFG_PSRT;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+ memctl->memc_psrt = CONFIG_SYS_PSRT;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
/* 60x SDRAM setup:
*/
- size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
- (uchar *) CFG_SDRAM_BASE);
- size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
- (uchar *) CFG_SDRAM_BASE);
+ size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+ size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
if (size8 < size9) {
psize = size9;
printf ("(60x:9COL) ");
} else {
- psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
- (uchar *) CFG_SDRAM_BASE);
+ psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
printf ("(60x:8COL) ");
}
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
icache_enable ();
@@ -380,10 +380,9 @@ phys_size_t initdram (int board_type)
}
#if defined(CONFIG_CMD_DOC)
-extern void doc_probe (ulong physadr);
void doc_init (void)
{
- doc_probe (CFG_DOC_BASE);
+ doc_probe (CONFIG_SYS_DOC_BASE);
}
#endif
diff --git a/board/atc/config.mk b/board/atc/config.mk
index eee7a60..dd854e7 100644
--- a/board/atc/config.mk
+++ b/board/atc/config.mk
@@ -25,7 +25,7 @@
# ATC boards
#
-# This should be equal to the CFG_FLASH_BASE define in config_atc.h
+# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_atc.h
# for the "final" configuration, with U-Boot in flash, or the address
# in RAM where U-Boot is loaded at for debugging.
#
diff --git a/board/atc/flash.c b/board/atc/flash.c
index 2ab60e8..fd76723 100644
--- a/board/atc/flash.c
+++ b/board/atc/flash.c
@@ -23,7 +23,7 @@
#include <common.h>
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
* has nothing to do with the flash chip being 8-bit or 16-bit.
@@ -67,11 +67,11 @@ unsigned long flash_init (void)
int i;
/* Init: no FLASHes known */
- for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+ for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
#if 0
ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
#else
- ulong flashbase = CFG_FLASH_BASE;
+ ulong flashbase = CONFIG_SYS_FLASH_BASE;
#endif
memset(&flash_info[i], 0, sizeof(flash_info_t));
@@ -87,20 +87,20 @@ unsigned long flash_init (void)
size += flash_info[i].size;
}
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
- flash_get_info(CFG_MONITOR_BASE));
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+ flash_get_info(CONFIG_SYS_MONITOR_BASE));
#endif
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
/* ENV protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- CFG_ENV_ADDR,
- CFG_ENV_ADDR+CFG_ENV_SIZE-1,
- flash_get_info(CFG_ENV_ADDR));
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1,
+ flash_get_info(CONFIG_ENV_ADDR));
#endif
@@ -164,13 +164,13 @@ static flash_info_t *flash_get_info(ulong base)
int i;
flash_info_t * info;
- for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
if (info->start[0] <= base && base < info->start[0] + info->size)
break;
}
- return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+ return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
}
/*-----------------------------------------------------------------------
@@ -476,7 +476,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
udelay (1000);
while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
if (intel) {
@@ -490,14 +490,14 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
}
/* show that we're waiting */
- if ((get_timer(last)) > CFG_HZ) {/* every second */
+ if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
putc ('.');
last = get_timer(0);
}
}
/* show that we're waiting */
- if ((get_timer(last)) > CFG_HZ) { /* every second */
+ if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
putc ('.');
last = get_timer(0);
}
@@ -601,7 +601,7 @@ static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
/* data polling for D7 */
while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW)0x00F000F0; /* reset bank */
res = 1;
}
@@ -647,7 +647,7 @@ static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
start = get_timer (0);
while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
*dest = (FPW)0x00B000B0; /* Suspend program */
res = 1;
}
diff --git a/board/atc/ti113x.c b/board/atc/ti113x.c
index e112eca..473bb10 100644
--- a/board/atc/ti113x.c
+++ b/board/atc/ti113x.c
@@ -526,8 +526,8 @@ int i82365_init (void)
mem.map = 0;
mem.flags = MAP_ATTRIB | MAP_ACTIVE;
mem.speed = 300;
- mem.sys_start = CFG_PCMCIA_MEM_ADDR;
- mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
+ mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
+ mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
@@ -613,8 +613,8 @@ static void i82365_dump_regions (pci_dev_t dev)
{
u_int tmp[2];
u_int *mem = (void *) socket.cb_phys;
- u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
- u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
+ u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
+ u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
pci_read_config_dword (dev, 0x00, tmp + 0);
pci_read_config_dword (dev, 0x80, tmp + 1);
generated by cgit v1.1 at 2024-11-22 19:01:51 +0000