diff options
Diffstat (limited to 'board/apollon/lowlevel_init.S')
| -rw-r--r-- | board/apollon/lowlevel_init.S | 248 |
1 files changed, 124 insertions, 124 deletions
diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S index f254428..8381fea 100644 --- a/board/apollon/lowlevel_init.S +++ b/board/apollon/lowlevel_init.S @@ -31,16 +31,16 @@ #include <asm/arch/clocks.h> #include "mem.h" -#define APOLLON_CS0_BASE 0x00000000 +#define APOLLON_CS0_BASE 0x00000000 #ifdef PRCM_CONFIG_I -#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907 -#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013 -#define SDRC_RFR_CTRL_0_VAL 0x00044C01 +#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907 +#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013 +#define SDRC_RFR_CTRL_0_VAL 0x00044C01 #elif defined(PRCM_CONFIG_II) -#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485 -#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C -#define SDRC_RFR_CTRL_0_VAL 0x00030001 +#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485 +#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C +#define SDRC_RFR_CTRL_0_VAL 0x00030001 #endif #define SDRAM_BASE_ADDRESS 0x80008000 @@ -66,100 +66,100 @@ flash_setup: ldr r1, =WD_UNLOCK2 str r1, [r0, #WSPR] - /* Pin muxing for SDRC */ - mov r1, #0x00 - ldr r0, =0x480000A1 /* ball C12, mode 0 */ - strb r1, [r0] - - ldr r0, =0x48000032 /* ball D11, mode 0 */ - strb r1, [r0] - - ldr r0, =0x480000A3 /* ball B13, mode 0 */ - strb r1, [r0] + /* Pin muxing for SDRC */ + mov r1, #0x00 + ldr r0, =0x480000A1 /* ball C12, mode 0 */ + strb r1, [r0] - /* SDRC setting */ - ldr r0, =OMAP2420_SDRC_BASE - ldr r1, =0x00000010 - str r1, [r0, #0x10] + ldr r0, =0x48000032 /* ball D11, mode 0 */ + strb r1, [r0] - ldr r1, =0x00000100 - str r1, [r0, #0x44] + ldr r0, =0x480000A3 /* ball B13, mode 0 */ + strb r1, [r0] - /* SDRC CS0 configuration */ - ldr r1, =0x00d04011 - str r1, [r0, #0x80] + /* SDRC setting */ + ldr r0, =OMAP2420_SDRC_BASE + ldr r1, =0x00000010 + str r1, [r0, #0x10] - ldr r1, =SDRC_ACTIM_CTRLA_0_VAL - str r1, [r0, #0x9C] + ldr r1, =0x00000100 + str r1, [r0, #0x44] - ldr r1, =SDRC_ACTIM_CTRLB_0_VAL - str r1, [r0, #0xA0] + /* SDRC CS0 configuration */ + ldr r1, =0x00d04011 + str r1, [r0, #0x80] - ldr r1, =SDRC_RFR_CTRL_0_VAL - str r1, [r0, #0xA4] + ldr r1, =SDRC_ACTIM_CTRLA_0_VAL + str r1, [r0, #0x9C] - ldr r1, =0x00000041 - str r1, [r0, #0x70] + ldr r1, =SDRC_ACTIM_CTRLB_0_VAL + str r1, [r0, #0xA0] - /* Manual command sequence */ - ldr r1, =0x00000007 - str r1, [r0, #0xA8] + ldr r1, =SDRC_RFR_CTRL_0_VAL + str r1, [r0, #0xA4] - ldr r1, =0x00000000 - str r1, [r0, #0xA8] + ldr r1, =0x00000041 + str r1, [r0, #0x70] - ldr r1, =0x00000001 - str r1, [r0, #0xA8] + /* Manual command sequence */ + ldr r1, =0x00000007 + str r1, [r0, #0xA8] - ldr r1, =0x00000002 - str r1, [r0, #0xA8] - str r1, [r0, #0xA8] + ldr r1, =0x00000000 + str r1, [r0, #0xA8] - /* - * CS0 SDRC Mode register - * Burst length = 4 - DDR memory - * Serial mode - * CAS latency = 3 - */ - ldr r1, =0x00000032 - str r1, [r0, #0x84] + ldr r1, =0x00000001 + str r1, [r0, #0xA8] - /* Note: You MUST set EMR values */ - /* EMR1 & EMR2 */ - ldr r1, =0x00000000 - str r1, [r0, #0x88] - str r1, [r0, #0x8C] + ldr r1, =0x00000002 + str r1, [r0, #0xA8] + str r1, [r0, #0xA8] + + /* + * CS0 SDRC Mode register + * Burst length = 4 - DDR memory + * Serial mode + * CAS latency = 3 + */ + ldr r1, =0x00000032 + str r1, [r0, #0x84] + + /* Note: You MUST set EMR values */ + /* EMR1 & EMR2 */ + ldr r1, =0x00000000 + str r1, [r0, #0x88] + str r1, [r0, #0x8C] #ifdef OLD_SDRC_DLLA_CTRL - /* SDRC_DLLA_CTRL */ - ldr r1, =0x00007306 - str r1, [r0, #0x60] + /* SDRC_DLLA_CTRL */ + ldr r1, =0x00007306 + str r1, [r0, #0x60] - ldr r1, =0x00007303 - str r1, [r0, #0x60] + ldr r1, =0x00007303 + str r1, [r0, #0x60] #else - /* SDRC_DLLA_CTRL */ - ldr r1, =0x00000506 - str r1, [r0, #0x60] + /* SDRC_DLLA_CTRL */ + ldr r1, =0x00000506 + str r1, [r0, #0x60] - ldr r1, =0x00000503 - str r1, [r0, #0x60] + ldr r1, =0x00000503 + str r1, [r0, #0x60] #endif #ifdef __BROKEN_FEATURE__ - /* SDRC_DLLB_CTRL */ - ldr r1, =0x00000506 - str r1, [r0, #0x68] + /* SDRC_DLLB_CTRL */ + ldr r1, =0x00000506 + str r1, [r0, #0x68] - ldr r1, =0x00000503 - str r1, [r0, #0x68] + ldr r1, =0x00000503 + str r1, [r0, #0x68] #endif - /* little delay after init */ - mov r2, #0x1800 + /* little delay after init */ + mov r2, #0x1800 1: - subs r2, r2, #0x1 - bne 1b + subs r2, r2, #0x1 + bne 1b /* Setup base address */ ldr r0, =0x00000000 /* NOR address */ @@ -178,21 +178,21 @@ copy_loop: #endif prcm_setup: - ldr r0, =OMAP2420_CM_BASE - ldr r1, [r0, #0x544] /* CLKSEL2_PLL */ - bic r1, r1, #0x03 - orr r1, r1, #0x02 - str r1, [r0, #0x544] - - ldr r1, [r0, #0x500] - bic r1, r1, #0x03 - orr r1, r1, #0x01 - str r1, [r0, #0x500] - - ldr r1, [r0, #0x140] - bic r1, r1, #0x1f - orr r1, r1, #0x02 - str r1, [r0, #0x140] + ldr r0, =OMAP2420_CM_BASE + ldr r1, [r0, #0x544] /* CLKSEL2_PLL */ + bic r1, r1, #0x03 + orr r1, r1, #0x02 + str r1, [r0, #0x544] + + ldr r1, [r0, #0x500] + bic r1, r1, #0x03 + orr r1, r1, #0x01 + str r1, [r0, #0x500] + + ldr r1, [r0, #0x140] + bic r1, r1, #0x1f + orr r1, r1, #0x02 + str r1, [r0, #0x140] #ifdef PRCM_CONFIG_I ldr r1, =0x000003C3 @@ -204,58 +204,58 @@ prcm_setup: ldr r1, =0x00000002 str r1, [r0, #0x340] - ldr r1, =CM_CLKSEL1_CORE + ldr r1, =CM_CLKSEL1_CORE #ifdef PRCM_CONFIG_I - ldr r2, =0x08300C44 + ldr r2, =0x08300C44 #else - ldr r2, =0x04600C26 + ldr r2, =0x04600C26 #endif - str r2, [r1] + str r2, [r1] - ldr r0, =OMAP2420_CM_BASE - ldr r1, [r0, #0x084] - and r1, r1, #0x01 - cmp r1, #0x01 - bne clkvalid + ldr r0, =OMAP2420_CM_BASE + ldr r1, [r0, #0x084] + and r1, r1, #0x01 + cmp r1, #0x01 + bne clkvalid - b . + b . clkvalid: - mov r1, #0x01 - str r1, [r0, #0x080] + mov r1, #0x01 + str r1, [r0, #0x080] waitvalid: - ldr r1, [r0, #0x084] - and r1, r1, #0x01 - cmp r1, #0x00 - bne waitvalid + ldr r1, [r0, #0x084] + and r1, r1, #0x01 + cmp r1, #0x00 + bne waitvalid - ldr r0, =CM_CLKSEL1_PLL + ldr r0, =CM_CLKSEL1_PLL #ifdef PRCM_CONFIG_I - ldr r1, =0x01837100 + ldr r1, =0x01837100 #else - ldr r1, =0x01832100 + ldr r1, =0x01832100 #endif - str r1, [r0] + str r1, [r0] - ldr r0, =PRCM_CLKCFG_CTRL - mov r1, #0x01 - str r1, [r0] - mov r6, #0x50 + ldr r0, =PRCM_CLKCFG_CTRL + mov r1, #0x01 + str r1, [r0] + mov r6, #0x50 loop1: - subs r6, r6, #0x01 - cmp r6, #0x01 - bne loop1 + subs r6, r6, #0x01 + cmp r6, #0x01 + bne loop1 - ldr r0, =CM_CLKEN_PLL + ldr r0, =CM_CLKEN_PLL mov r1, #0x0f - str r1, [r0] + str r1, [r0] - mov r6, #0x100 + mov r6, #0x100 loop2: - subs r6, r6, #0x01 - cmp r6, #0x01 - bne loop2 + subs r6, r6, #0x01 + cmp r6, #0x01 + bne loop2 ldr r0, =0x48008200 ldr r1, =0xbfffffff |