diff options
Diffstat (limited to 'board/amcc')
| -rw-r--r-- | board/amcc/acadia/config.mk | 2 | ||||
| -rw-r--r-- | board/amcc/acadia/cpr.c | 6 | ||||
| -rw-r--r-- | board/amcc/acadia/flash.c | 10 | ||||
| -rw-r--r-- | board/amcc/acadia/memory.c | 14 |
4 files changed, 10 insertions, 22 deletions
diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk index 79b948e..ce21374 100644 --- a/board/amcc/acadia/config.mk +++ b/board/amcc/acadia/config.mk @@ -33,7 +33,7 @@ endif ifeq ($(CONFIG_SPI_U_BOOT),y) LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-spi.lds -PAD_TO = 0x00840000 +PAD_TO = 0x00840000 endif ifeq ($(debug),1) diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/cpr.c index 10d8290..23b9e12 100644 --- a/board/amcc/acadia/cpr.c +++ b/board/amcc/acadia/cpr.c @@ -184,9 +184,9 @@ unsigned long get_tbclk (void) /* * Determine FBK_DIV. */ - pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); - if (pllFbkDiv == 0) - pllFbkDiv = 256; + pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); + if (pllFbkDiv == 0) + pllFbkDiv = 256; freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; diff --git a/board/amcc/acadia/flash.c b/board/amcc/acadia/flash.c index 39a11f9..0626aba 100644 --- a/board/amcc/acadia/flash.c +++ b/board/amcc/acadia/flash.c @@ -727,7 +727,7 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) } #endif /* TODO: remove ifdef when Flash responds correctly */ - /* + /* * TODO: Start * uncomment block above when Flash responds correctly. * also remove the lines below: @@ -847,7 +847,7 @@ static int wait_for_DQ7_2(flash_info_t * info, int sect) last = start; while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != (CFG_FLASH_WORD_SIZE) 0x00800080) { - DEBUGF("DQ7_2: start = 0x%08lx, now = 0x%08lx\n", start, now); + DEBUGF("DQ7_2: start = 0x%08lx, now = 0x%08lx\n", start, now); if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { printf("Timeout\n"); return -1; @@ -871,7 +871,7 @@ static int wait_for_DQ7_2(flash_info_t * info, int sect) static void wr_flash_cmd(ulong sector, ushort addr, CFG_FLASH_WORD_SIZE value) { int fw_size; - + fw_size = sizeof(value); switch (fw_size) { @@ -991,8 +991,8 @@ static int flash_erase_2(flash_info_t * info, int s_first, int s_last) addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ printf(" done\n"); - - if (count > 0) { + + if (count > 0) { return 0; } else { return 1; diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 0f1de71..a1b0155 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -55,7 +55,6 @@ void sdram_init(void) if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) { mtspr(SPRG7, LOAK_NONE); /* "NONE" */ } - #if 1 /* * When running the NAND SPL, the normal EBC configuration is not @@ -77,7 +76,6 @@ void sdram_init(void) mtspr(SPRG6, LOAK_SPL); /* "SPL " */ mtspr(SPRG7, LOAK_OCM); /* "OCM " */ #endif - return; } @@ -98,14 +96,12 @@ static void cram_bcr_write(u32 wr_val) wr_val = wr_val << 2; /* wr_val = 0x1c048; */ - /* * # stop PLL clock before programming CRAM * set EPLD0_MUX_CTL.OESPR3 = 1 * delay 2 */ - /* * # CS1 * read 0x00200000 @@ -147,7 +143,6 @@ static void cram_bcr_write(u32 wr_val) * set EPLD0_MUX_CTL.OESPR3 = 0 */ - /* * set CRAMCR = 0x1 */ @@ -254,9 +249,6 @@ static u32 is_cram(void) gpio_reg = in32(GPIO1_OR); out32(GPIO1_OR, gpio_reg | 0x00000400); - - - /* Read Version ID */ cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR); udelay(100000); @@ -309,8 +301,7 @@ static long int cram_init(u32 already_inited) * In the case of NAND boot and SPI boot, CRAM will already be * initialized by the pre-loader */ - if (already_inited != 1) - { + if (already_inited != 1) { /* * #o CRAM Card * # - CRAMCRE @reg16 = 1; for CRAM to use @@ -323,7 +314,6 @@ static long int cram_init(u32 already_inited) * #end */ - /* * #1. EBC need to program READY, CLK, ADV for ASync mode * # config output @@ -448,8 +438,6 @@ static long int cram_init(u32 already_inited) /* * set EPLD0_MUX_CTL.OESPR3 = 0 */ - - mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */ } /* if (already_inited != 1) */ |