diff options
Diffstat (limited to 'board/amcc')
| -rw-r--r-- | board/amcc/bamboo/bamboo.c | 32 | ||||
| -rw-r--r-- | board/amcc/canyonlands/canyonlands.c | 22 | ||||
| -rw-r--r-- | board/amcc/ebony/ebony.c | 22 | ||||
| -rw-r--r-- | board/amcc/katmai/katmai.c | 22 | ||||
| -rw-r--r-- | board/amcc/luan/epld.h | 22 | ||||
| -rw-r--r-- | board/amcc/luan/luan.c | 22 | ||||
| -rw-r--r-- | board/amcc/ocotea/ocotea.c | 22 | ||||
| -rw-r--r-- | board/amcc/sequoia/sequoia.c | 28 | ||||
| -rw-r--r-- | board/amcc/taishan/showinfo.c | 112 | ||||
| -rw-r--r-- | board/amcc/taishan/taishan.c | 22 | ||||
| -rw-r--r-- | board/amcc/yosemite/yosemite.c | 32 | ||||
| -rw-r--r-- | board/amcc/yucca/yucca.c | 22 |
12 files changed, 190 insertions, 190 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 38186a5..2598f2c 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -542,22 +542,22 @@ void pci_target_init(struct pci_controller *hose) | Use byte reversed out routines to handle endianess. | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /*--------------------------------------------------------------------------+ * Set up Configuration registers diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 9495b62..91fae19 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -339,27 +339,27 @@ void pci_target_init(struct pci_controller * hose ) /* * Disable everything */ - out_le32((void *)PCIX0_PIM0SA, 0); /* disable */ - out_le32((void *)PCIX0_PIM1SA, 0); /* disable */ - out_le32((void *)PCIX0_PIM2SA, 0); /* disable */ - out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */ + out_le32((void *)PCIL0_PIM0SA, 0); /* disable */ + out_le32((void *)PCIL0_PIM1SA, 0); /* disable */ + out_le32((void *)PCIL0_PIM2SA, 0); /* disable */ + out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */ /* * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. */ - out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out_le32((void *)PCIX0_PIM0LAH, 0); - out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); - out_le32((void *)PCIX0_BAR0, 0); + out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); + out_le32((void *)PCIL0_PIM0LAH, 0); + out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); + out_le32((void *)PCIL0_BAR0, 0); /* * Program the board's subsystem id/vendor id */ - out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); + out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); + out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index e61b5de..0ca1acc 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -210,28 +210,28 @@ void pci_target_init(struct pci_controller *hose) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0SA, 0); /* disable */ - out32r(PCIX0_PIM1SA, 0); /* disable */ - out32r(PCIX0_PIM2SA, 0); /* disable */ - out32r(PCIX0_EROMBA, 0); /* disable expansion rom */ + out32r(PCIL0_PIM0SA, 0); /* disable */ + out32r(PCIL0_PIM1SA, 0); /* disable */ + out32r(PCIL0_PIM2SA, 0); /* disable */ + out32r(PCIL0_EROMBA, 0); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out32r(PCIX0_PIM0LAH, 0); - out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); + out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); + out32r(PCIL0_PIM0LAH, 0); + out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - out32r(PCIX0_BAR0, 0); + out32r(PCIL0_BAR0, 0); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); + out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); + out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index aa6d0ab..908f1a5 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -305,27 +305,27 @@ void pci_target_init(struct pci_controller * hose ) /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*-------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_BAR0, 0 ); /*-------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *-------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h index 05362e0..569d78c 100644 --- a/board/amcc/luan/epld.h +++ b/board/amcc/luan/epld.h @@ -8,8 +8,8 @@ #define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */ #define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */ -#define EPLD1_PCIX0_CNTL1 0x40 /* S*0 of 9531 */ -#define EPLD1_PCIX0_CNTL2 0x20 /* S*1 of 9531 */ +#define EPLD1_PCIL0_CNTL1 0x40 /* S*0 of 9531 */ +#define EPLD1_PCIL0_CNTL2 0x20 /* S*1 of 9531 */ #define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */ #define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */ #define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */ @@ -29,25 +29,25 @@ #define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */ #define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */ -#define EPLD4_PCIX0_VTH1 0x80 /* PCI-X 0 VTH1 status */ -#define EPLD4_PCIX0_VTH2 0x40 /* PCI-X 0 VTH2 status */ -#define EPLD4_PCIX0_VTH3 0x20 /* PCI-X 0 VTH3 status */ -#define EPLD4_PCIX0_VTH4 0x10 /* PCI-X 0 VTH4 status */ +#define EPLD4_PCIL0_VTH1 0x80 /* PCI-X 0 VTH1 status */ +#define EPLD4_PCIL0_VTH2 0x40 /* PCI-X 0 VTH2 status */ +#define EPLD4_PCIL0_VTH3 0x20 /* PCI-X 0 VTH3 status */ +#define EPLD4_PCIL0_VTH4 0x10 /* PCI-X 0 VTH4 status */ #define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */ #define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */ #define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */ #define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */ -#define EPLD5_PCIX0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */ -#define EPLD5_PCIX0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */ -#define EPLD5_PCIX0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */ -#define EPLD5_PCIX0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */ +#define EPLD5_PCIL0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */ +#define EPLD5_PCIL0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */ +#define EPLD5_PCIL0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */ +#define EPLD5_PCIL0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */ #define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */ #define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */ #define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */ #define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */ -#define EPLD6_PCIX0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */ +#define EPLD6_PCIL0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */ #define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */ #define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */ #define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */ diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 5f76672..a04f2af 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -173,28 +173,28 @@ void pci_target_init(struct pci_controller *hose) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_BAR0, 0 ); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index d776eda..0aa317e 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -321,28 +321,28 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_BAR0, 0 ); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 17f831c..d42c802 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -428,26 +428,26 @@ void pci_target_init(struct pci_controller *hose) * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /* * Set up Configuration registers diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c index e4e441b..a9a80e5 100644 --- a/board/amcc/taishan/showinfo.c +++ b/board/amcc/taishan/showinfo.c @@ -39,13 +39,13 @@ void show_reset_reg(void) mfcpr(CPR0_PLLD,reg); printf("cpr_plld = %#010lx\n",reg); - mfcpr(CPR0_PRIMAD,reg); + mfcpr(CPR0_PRIMAD0,reg); printf("cpr_primad = %#010lx\n",reg); - mfcpr(CPR0_PRIMBD,reg); + mfcpr(CPR0_PRIMBD0,reg); printf("cpr_primbd = %#010lx\n",reg); - mfcpr(CPR0_OPBD,reg); + mfcpr(CPR0_OPBD0,reg); printf("cpr_opbd = %#010lx\n",reg); mfcpr(CPR0_PERD,reg); @@ -106,59 +106,59 @@ void show_xbridge_info(void) printf("SDR0_XPLLD = %#010lx\n", reg); printf("PCI-X Bridge Configure registers\n"); - printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID)); - printf("PCIX0_DEVID = %#06x\n", in16r(PCIX0_DEVID)); - printf("PCIX0_CMD = %#06x\n", in16r(PCIX0_CMD)); - printf("PCIX0_STATUS = %#06x\n", in16r(PCIX0_STATUS)); - printf("PCIX0_REVID = %#04x\n", in8(PCIX0_REVID)); - printf("PCIX0_CACHELS = %#04x\n", in8(PCIX0_CACHELS)); - printf("PCIX0_LATTIM = %#04x\n", in8(PCIX0_LATTIM)); - printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE)); - printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST)); - - printf("PCIX0_BAR0 = %#010lx\n", in32r(PCIX0_BAR0)); - printf("PCIX0_BAR1 = %#010lx\n", in32r(PCIX0_BAR1)); - printf("PCIX0_BAR2 = %#010lx\n", in32r(PCIX0_BAR2)); - printf("PCIX0_BAR3 = %#010lx\n", in32r(PCIX0_BAR3)); - printf("PCIX0_BAR4 = %#010lx\n", in32r(PCIX0_BAR4)); - printf("PCIX0_BAR5 = %#010lx\n", in32r(PCIX0_BAR5)); - - printf("PCIX0_CISPTR = %#010lx\n", in32r(PCIX0_CISPTR)); - printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID)); - printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID)); - printf("PCIX0_EROMBA = %#010lx\n", in32r(PCIX0_EROMBA)); - printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP)); - printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN)); - printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN)); - printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT)); - printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY)); - - printf("PCIX0_BRDGOPT1 = %#010lx\n", in32r(PCIX0_BRDGOPT1)); - printf("PCIX0_BRDGOPT2 = %#010lx\n", in32r(PCIX0_BRDGOPT2)); - - printf("PCIX0_POM0LAL = %#010lx\n", in32r(PCIX0_POM0LAL)); - printf("PCIX0_POM0LAH = %#010lx\n", in32r(PCIX0_POM0LAH)); - printf("PCIX0_POM0SA = %#010lx\n", in32r(PCIX0_POM0SA)); - printf("PCIX0_POM0PCILAL = %#010lx\n", in32r(PCIX0_POM0PCIAL)); - printf("PCIX0_POM0PCILAH = %#010lx\n", in32r(PCIX0_POM0PCIAH)); - printf("PCIX0_POM1LAL = %#010lx\n", in32r(PCIX0_POM1LAL)); - printf("PCIX0_POM1LAH = %#010lx\n", in32r(PCIX0_POM1LAH)); - printf("PCIX0_POM1SA = %#010lx\n", in32r(PCIX0_POM1SA)); - printf("PCIX0_POM1PCILAL = %#010lx\n", in32r(PCIX0_POM1PCIAL)); - printf("PCIX0_POM1PCILAH = %#010lx\n", in32r(PCIX0_POM1PCIAH)); - printf("PCIX0_POM2SA = %#010lx\n", in32r(PCIX0_POM2SA)); - - printf("PCIX0_PIM0SA = %#010lx\n", in32r(PCIX0_PIM0SA)); - printf("PCIX0_PIM0LAL = %#010lx\n", in32r(PCIX0_PIM0LAL)); - printf("PCIX0_PIM0LAH = %#010lx\n", in32r(PCIX0_PIM0LAH)); - printf("PCIX0_PIM1SA = %#010lx\n", in32r(PCIX0_PIM1SA)); - printf("PCIX0_PIM1LAL = %#010lx\n", in32r(PCIX0_PIM1LAL)); - printf("PCIX0_PIM1LAH = %#010lx\n", in32r(PCIX0_PIM1LAH)); - printf("PCIX0_PIM2SA = %#010lx\n", in32r(PCIX0_PIM1SA)); - printf("PCIX0_PIM2LAL = %#010lx\n", in32r(PCIX0_PIM1LAL)); - printf("PCIX0_PIM2LAH = %#010lx\n", in32r(PCIX0_PIM1LAH)); - - printf("PCIX0_XSTS = %#010lx\n", in32r(PCIX0_STS)); + printf("PCIL0_VENDID = %#06x\n", in16r(PCIL0_VENDID)); + printf("PCIL0_DEVID = %#06x\n", in16r(PCIL0_DEVID)); + printf("PCIL0_CMD = %#06x\n", in16r(PCIL0_CMD)); + printf("PCIL0_STATUS = %#06x\n", in16r(PCIL0_STATUS)); + printf("PCIL0_REVID = %#04x\n", in8(PCIL0_REVID)); + printf("PCIL0_CACHELS = %#04x\n", in8(PCIL0_CACHELS)); + printf("PCIL0_LATTIM = %#04x\n", in8(PCIL0_LATTIM)); + printf("PCIL0_HDTYPE = %#04x\n", in8(PCIL0_HDTYPE)); + printf("PCIL0_BIST = %#04x\n", in8(PCIL0_BIST)); + + printf("PCIL0_BAR0 = %#010lx\n", in32r(PCIL0_BAR0)); + printf("PCIL0_BAR1 = %#010lx\n", in32r(PCIL0_BAR1)); + printf("PCIL0_BAR2 = %#010lx\n", in32r(PCIL0_BAR2)); + printf("PCIL0_BAR3 = %#010lx\n", in32r(PCIL0_BAR3)); + printf("PCIL0_BAR4 = %#010lx\n", in32r(PCIL0_BAR4)); + printf("PCIL0_BAR5 = %#010lx\n", in32r(PCIL0_BAR5)); + + printf("PCIL0_CISPTR = %#010lx\n", in32r(PCIL0_CISPTR)); + printf("PCIL0_SBSSYSVID = %#010x\n", in16r(PCIL0_SBSYSVID)); + printf("PCIL0_SBSSYSID = %#010x\n", in16r(PCIL0_SBSYSID)); + printf("PCIL0_EROMBA = %#010lx\n", in32r(PCIL0_EROMBA)); + printf("PCIL0_CAP = %#04x\n", in8(PCIL0_CAP)); + printf("PCIL0_INTLN = %#04x\n", in8(PCIL0_INTLN)); + printf("PCIL0_INTPN = %#04x\n", in8(PCIL0_INTPN)); + printf("PCIL0_MINGNT = %#04x\n", in8(PCIL0_MINGNT)); + printf("PCIL0_MAXLTNCY = %#04x\n", in8(PCIL0_MAXLTNCY)); + + printf("PCIL0_BRDGOPT1 = %#010lx\n", in32r(PCIL0_BRDGOPT1)); + printf("PCIL0_BRDGOPT2 = %#010lx\n", in32r(PCIL0_BRDGOPT2)); + + printf("PCIL0_POM0LAL = %#010lx\n", in32r(PCIL0_POM0LAL)); + printf("PCIL0_POM0LAH = %#010lx\n", in32r(PCIL0_POM0LAH)); + printf("PCIL0_POM0SA = %#010lx\n", in32r(PCIL0_POM0SA)); + printf("PCIL0_POM0PCILAL = %#010lx\n", in32r(PCIL0_POM0PCIAL)); + printf("PCIL0_POM0PCILAH = %#010lx\n", in32r(PCIL0_POM0PCIAH)); + printf("PCIL0_POM1LAL = %#010lx\n", in32r(PCIL0_POM1LAL)); + printf("PCIL0_POM1LAH = %#010lx\n", in32r(PCIL0_POM1LAH)); + printf("PCIL0_POM1SA = %#010lx\n", in32r(PCIL0_POM1SA)); + printf("PCIL0_POM1PCILAL = %#010lx\n", in32r(PCIL0_POM1PCIAL)); + printf("PCIL0_POM1PCILAH = %#010lx\n", in32r(PCIL0_POM1PCIAH)); + printf("PCIL0_POM2SA = %#010lx\n", in32r(PCIL0_POM2SA)); + + printf("PCIL0_PIM0SA = %#010lx\n", in32r(PCIL0_PIM0SA)); + printf("PCIL0_PIM0LAL = %#010lx\n", in32r(PCIL0_PIM0LAL)); + printf("PCIL0_PIM0LAH = %#010lx\n", in32r(PCIL0_PIM0LAH)); + printf("PCIL0_PIM1SA = %#010lx\n", in32r(PCIL0_PIM1SA)); + printf("PCIL0_PIM1LAL = %#010lx\n", in32r(PCIL0_PIM1LAL)); + printf("PCIL0_PIM1LAH = %#010lx\n", in32r(PCIL0_PIM1LAH)); + printf("PCIL0_PIM2SA = %#010lx\n", in32r(PCIL0_PIM1SA)); + printf("PCIL0_PIM2LAL = %#010lx\n", in32r(PCIL0_PIM1LAL)); + printf("PCIL0_PIM2LAH = %#010lx\n", in32r(PCIL0_PIM1LAH)); + + printf("PCIL0_XSTS = %#010lx\n", in32r(PCIL0_STS)); } int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 4a0573e..0c20faf 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -254,28 +254,28 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_BAR0, 0 ); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 1ec13eb..7ceccfa 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -408,22 +408,22 @@ void pci_target_init(struct pci_controller *hose) | Use byte reversed out routines to handle endianess. | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /*--------------------------------------------------------------------------+ * Set up Configuration registers diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 5c9d491..d8f4bcb 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -633,27 +633,27 @@ void pci_target_init(struct pci_controller * hose ) /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*-------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_BAR0, 0 ); /*-------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *-------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ |